UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 304

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

11.4.2 Setting overflow time of watchdog timer
starts counting again by writing “ACH” to WDTE during the window open period before the overflow time.
304
Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer
The following overflow time is set.
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0
Remarks 1. f
5. The watchdog timer continues its operation during self-programming and EEPROM
WDCS2
depending on the set value of bit 0 (LSROSC) of the option byte.
If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is not cleared to 0 but starts counting from the value at
which it was stopped.
If oscillation of the internal low-speed oscillator is stopped by setting LSRSTOP (bit 1 of the
internal oscillation mode register (RCM) = 1) when LSROSC = 0, the watchdog timer stops
operating. At this time, the counter is not cleared to 0.
emulation of the flash memory.
delayed. Set the overflow time and window size taking this delay into consideration.
In HALT mode
In STOP mode
0
0
0
0
1
1
1
1
2. ( ): f
2. The watchdog timer continues its operation during self-programming and EEPROM
RL
is prohibited.
emulation of the flash memory. During processing, the interrupt acknowledge time
is delayed.
consideration.
: Internal low-speed oscillation clock frequency
Table 11-3. Setting of Overflow Time of Watchdog Timer
WDCS1
RL
0
0
1
1
0
0
1
1
= 264 kHz (MAX.)
Watchdog timer operation stops.
Oscillator Can Be Stopped by Software)
CHAPTER 11 WATCHDOG TIMER
WDCS0
Set the overflow time and window size taking this delay into
LSROSC = 0 (Internal Low-Speed
0
1
0
1
0
1
0
1
User’s Manual U17260EJ6V0UD
2
2
2
2
2
2
2
2
10
11
12
13
14
15
16
17
During processing, the interrupt acknowledge time is
/f
/f
/f
/f
/f
/f
/f
/f
RL
RL
RL
RL
RL
RL
RL
RL
(3.88 ms)
(7.76 ms)
(15.52 ms)
(31.03 ms)
(62.06 ms)
(124.12 ms)
(248.24 ms)
(496.48 ms)
Overflow Time of Watchdog Timer
Watchdog timer operation continues.
LSROSC = 1 (Internal Low-Speed
Oscillator Cannot Be Stopped)