UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 490

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

490
Address: FF66H, FF67H
Symbol
MDB0
(3) Multiplication/division data register B0 (MDB0)
Cautions 1. Do not change the value of MDB0 during operation processing (while bit 7 (DMUE) of
CHAPTER 18 MULTIPLIER/DIVIDER (
The functions of MDA0 when an operation is executed are shown in the table below.
The register configuration differs between when multiplication is executed and when division is executed, as
follows.
• Register configuration during multiplication
• Register configuration during division
MDA0 fetches the calculation result as soon as the clock is input, when bit 7 (DMUE) of multiplier/divider
control register 0 (DMUC0) is set to 1.
MDA0H and MDA0L can be set by an 8-bit or 16-bit memory manipulation instruction.
Reset signal generation clears MDA0H and MDA0L to 0000H.
MDB0 is a register that stores a 16-bit multiplier B in the multiplication mode and a 16-bit divisor in the
division mode.
MDB0 can be set by an 8-bit or 16-bit memory manipulation instruction.
Reset signal generation sets MDB0 to 0000H.
MDA0 (bits 15 to 0) × MDB0 (bits 15 to 0) = MDA0 (bits 31 to 0)
MDA0 (bits 31 to 0) ÷ MDB0 (bits 15 to 0) = MDA0 (bits 31 to 0) … SDR0 (bits 15 to 0)
MDB
015
DMUSEL0
<Multiplier A>
<Dividend>
2. Do not clear MDB0 to 0000H in the division mode. If set, undefined operation results are
0
1
multiplier/divider control register 0 (DMUC0) is 1).
executed, but the result is undefined.
stored in MDA0 and SDR0.
MDB
014
Figure 18-4. Format of Multiplication/Division Data Register B0 (MDB0)
MDB
013
Table 18-2. Functions of MDA0 During Operation Execution
After reset: 0000H
FF67H (MDB0H)
Division mode
Multiplication mode
MDB
012
<Multiplier B>
<Divisor>
Operation Mode
MDB
011
MDB
010
User’s Manual U17260EJ6V0UD
PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY)
R/W
MDB
009
<Product>
<Quotient>
MDB
008
Dividend
Higher 16 bits: 0, Lower 16
bits: Multiplier A
MDB
007
MDB
Setting
006
MDB
005
Even in this case, the operation is
<Remainder>
FF66H (MDB0L)
MDB
004
MDB
003
Division result (quotient)
Multiplication result
(product)
MDB
Operation Result
002
MDB
001
MDB
000