UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 517

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

21.1 Standby Function and Configuration
21.1.1 Standby function
available.
(1) HALT mode
(2) STOP mode
set are held. The I/O port output latches and output buffer statuses are also held.
21.1.2 Registers controlling standby function
The standby function is designed to reduce the operating current of the system. The following two modes are
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is
Cautions 1. The STOP mode can be used only when the CPU is operating on the main system clock. The
The standby function is controlled by the following two registers.
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
Remark For the registers that start, stop, or select the clock, see CHAPTER 6 CLOCK GENERATOR.
HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the
high-speed system clock oscillator, internal high-speed oscillator, internal low-speed oscillator, or subsystem
clock oscillator is operating before the HALT mode is set, oscillation of each clock continues. In this mode, the
operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting
operation immediately upon interrupt request generation and carrying out intermittent operations frequently.
STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator and
internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the CPU operating
current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is
released when the X1 clock is selected, select the HALT mode if it is necessary to start processing immediately
upon interrupt request generation.
2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation
3. The following sequence is recommended for operating current reduction of the A/D converter
subsystem clock oscillation cannot be stopped. The HALT mode can be used when the CPU
is operating on either the main system clock or the subsystem clock.
operating with main system clock before executing STOP instruction.
when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D
converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute
the STOP instruction.
CHAPTER 21 STANDBY FUNCTION
User’s Manual U17260EJ6V0UD
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