UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 229

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

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7.4.6 PPG output operation
(Programmable Pulse Generator) signal during a cycle set by CR00n when bits 3 and 2 (TMC0n3 and TMC0n2) of 16-
bit timer mode control register 0n (TMC0n) are set to 11 (clear & start upon a match between TM0n and CR00n).
A square wave having a pulse width set in advance by CR01n is output from the TO0n pin as a PPG
The pulse cycle and duty factor of the pulse generated as the PPG output are as follows.
• Pulse cycle = (Set value of CR00n + 1) × Count clock cycle
• Duty = (Set value of CR01n + 1) / (Set value of CR00n + 1)
Caution To change the duty factor (value of CR01n) during operation, see 7.5.1 Rewriting CR01n during
Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0).
Remark n = 0:
Count clock
TM0n operation.
2. For how to enable the INTTM00n signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS.
n = 0, 1:
TMC0n3, TMC0n2
Operable bits
µ
µ
PD78F0531, 78F0532, 78F0533
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-45. Block Diagram of PPG Output Operation
Compare register
Timer counter
User’s Manual U17260EJ6V0UD
Match signal
(CR01n)
(TM0n)
Compare register
Clear
(CR00n)
Match signal
controller
Output
TO0n output
Interrupt signal
(INTTM00n)
Interrupt signal
(INTTM01n)
TO0n pin
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