UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 415
UPD78F0537DGA(T)-9EV-A
Manufacturer Part Number
UPD78F0537DGA(T)-9EV-A
Description
8BIT MCU, 128K FLASH, 7KB RAM, SMD
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0537DGA(T)-9EV-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
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17.1 Functions of Serial Interface IIC0
Serial interface IIC0 has the following two modes.
(1) Operation stop mode
(2) I
Figure 17-1 shows a block diagram of serial interface IIC0.
This mode is used when serial transfers are not performed. It can therefore be used to reduce power
consumption.
This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCL0) line and a
serial data bus (SDA0) line.
This mode complies with the I
“transfer direction specification”, “data”, and “stop condition” data to the slave device, via the serial data bus.
The slave device automatically detects these received status and data by hardware. This function can simplify
the part of application program that controls the I
Since the SCL0 and SDA0 pins are used for open drain outputs, IIC0 requires pull-up resistors for the serial
clock line and the serial data bus line.
Caution Do not use serial interface IIC0 and the multiplier/divider simultaneously, because various
2
C bus mode (multimaster supported)
flags corresponding to interrupt request sources are shared among serial interface IIC0 and
the multiplier/divider.
CHAPTER 17 SERIAL INTERFACE IIC0
2
C bus format and the master device can generated “start condition”, “address”,
User’s Manual U17260EJ6V0UD
2
C bus.
415
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