UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 132

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(2) Port registers (P0 to P7, P12 to P14)
132
Symbol
P12
P13
P14
Note “0” is always read from the output latch of P121 to P124 if the pin is in the external clock input mode.
These registers write the data that is output from the chip when data is output from a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output
latch is read.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to 00H.
P0
P1
P2
P3
P4
P5
P6
P7
P17
P27
P77
Pmn
7
0
0
0
0
0
0
1
0
0
0
Output 0
Output 1
P06
P16
P26
P76
0
6
0
0
0
0
0
0
Output data control (in output mode)
P05
P15
P25
P75
5
0
0
0
0
0
0
0
P124
Figure 5-27. Format of Port Register
P04
P14
P24
P74
4
0
0
0
0
0
0
CHAPTER 5 PORT FUNCTIONS
Note
User’s Manual U17260EJ6V0UD
P123
P03
P13
P23
P33
P43
P53
P63
P73
3
0
0
Note
m = 0 to 7, 12 to 14; n = 0 to 7
P122
P02
P12
P22
P32
P42
P52
P62
P72
2
0
0
Note
P121
P141
P01
P11
P21
P31
P41
P51
P61
P71
1
0
Input low level
Input high level
Note
P120
P130
P140
P00
P10
P20
P30
P40
P50
P60
P70
0
Input data read (in input mode)
Address
FF0CH
FF0DH
FF00H
FF01H
FF02H
FF03H
FF04H
FF05H
FF06H
FF07H
FF0EH
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
After reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W