UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 440

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

to IIC shift register 0 (IIC0), and the transmitting side cancels the wait state when data is written to IIC0.
440
Transfer lines
(2) When master and slave devices both have a nine-clock wait
Remark
A wait may be automatically generated depending on the setting of bit 3 (WTIM0) of IIC control register 0 (IICC0).
Normally, the receiving side cancels the wait state when bit 5 (WREL0) of IICC0 is set to 1 or when FFH is written
The master device can also cancel the wait state via either of the following methods.
• By setting bit 1 (STT0) of IICC0 to 1
• By setting bit 0 (SPT0) of IICC0 to 1
Master
Slave
(master transmits, slave receives, and ACKE0 = 1)
ACKE0: Bit 2 of IIC control register 0 (IICC0)
WREL0: Bit 5 of IIC control register 0 (IICC0)
ACKE0
SDA0
SCL0
SCL0
SCL0
IIC0
IIC0
H
Generate according to previously set ACKE0 value
D2
6
6
Master and slave both wait
after output of ninth clock
D1
7
7
CHAPTER 17 SERIAL INTERFACE IIC0
D0
8
8
User’s Manual U17260EJ6V0UD
Figure 17-18. Wait (2/2)
ACK
9
9
Wait from
master and
slave
Wait from slave
IIC0 data write (cancel wait)
1
D7
1
FFH is written to IIC0 or WREL0 is set to 1
D6
2
2
D5
3
3