UPD30181GM-66-8ED NEC, UPD30181GM-66-8ED Datasheet
UPD30181GM-66-8ED
Available stocks
Related parts for UPD30181GM-66-8ED
UPD30181GM-66-8ED Summary of contents
Page 1
... User’s Manual V 4181™ R 64-/32-Bit Microprocessor Hardware µ µ µ µ PD30181 Document No. U14272EJ3V0UM00 (3rd edition) Date Published November 2002 NS CP(K) NEC Electronics Corporation 2000 MIPS Technologies, Inc. 1998 Printed in Japan ...
Page 2
User’s Manual U14272EJ3V0UM ...
Page 3
... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
Page 4
... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • ...
Page 5
... Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • ...
Page 6
... Addition of description for IRDIN/RxD2 in 2.2.10 IrDA interface signals Addition and modification in 2.3 Pin Status in Specific Status Addition of 2.4 Recommended Connection of Unused Pins and I/O Circuit Types and 2.5 Pin I/O Circuits pp Addition of CHAPTER 3 CP0 REGISTERS p. 95 Modification of Table 4-6. DRAM Address Map p ...
Page 7
... Major Revisions in This Edition (2/5) Page p. 119 Modification of description in 6.3.2 Connection to external ROM (x 16) devices p. 122 Modification of Remark in 6.3.3 (4) 64 Mbit PageROM p. 123 Modification of figure in 6.3.3 (5) 32 Mbit flash memory (when using Intel Modification of Figure 6-3 through Figure 6-8 pp. 125 to 128, 130 p. 129 Addition of description in Table 6- 134 Addition of Caution and modification in Remark in 6 ...
Page 8
Page p. 198 Modification of description of Cautions in 10.5.4 Activation via DCD interrupt request pp. 201 to 204 Modification of descriptions in 10.6.1 through 10.6.4 pp. 205 to 207 Addition of 10.6.5 through 10.6.8 Modification of description for bit ...
Page 9
Major Revisions in This Edition (4/5) Page p. 333 Modification of signal names in Figure 17-1. CompactFlash Interrupt Logic p. 333 Modification of description for bit 0 in 17.3.3 CFG_REG_1 (0x0B00 08FE) p. 336 Addition of Caution for bit 4 ...
Page 10
Page p. 399 Modification of description in 21.1.1 LCD interface p. 401 Modification of bus width in Figure 21-1. LCD Controller Block Diagram p. 406 Modification of description in 21.3.4 Frame buffer memory and FIFO Addition of Remark in 21.4.11 ...
Page 11
Readers This manual targets users who intend to understand the functions of the V to design application systems using this microprocessor. Purpose This manual introduces the hardware functions of the V organization described below. Organization Two manuals are available for ...
Page 12
Related Documents When using this manual, also refer to the following documents. V 4181 Hardware User’s Manual R µ PD30181 (V V 4100 Series Architecture User’s Manual R V Series R The related documents indicated here may include preliminary version. ...
Page 13
CHAPTER 1 INTRODUCTION ............................................................................................................. 29 1.1 Features .................................................................................................................................... 29 1.2 Ordering Information ............................................................................................................... 30 1.3 V 4181 Key Features ............................................................................................................... 30 R 1.3.1 CPU core ..................................................................................................................................... 1.3.2 Bus interface ............................................................................................................................... 1.3.3 Memory interface ......................................................................................................................... 1.3.4 DMA controller (DCU) .................................................................................................................. 1.3.5 ...
Page 14
... Serial interface channel 1 signals ................................................................................................ 2.2.10 IrDA interface signals ................................................................................................................ 2.2.11 General-purpose I/O signals ...................................................................................................... 2.2.12 Dedicated V /GND signals ...................................................................................................... DD 2.3 Pin Status in Specific Status .................................................................................................. 60 2.4 Recommended Connection of Unused Pins and I/O Circuit Types .................................... 63 2.5 Pin I/O Circuits ......................................................................................................................... 66 CHAPTER 3 CP0 REGISTERS ............................................................................................................ 67 3.1 Coprocessor 0 (CP0) ............................................................................................................... 67 3.2 Details of CP0 Registers ......................................................................................................... 69 3.2.1 Index register (0) ......................................................................................................................... 3.2.2 Random register (1) ..................................................................................................................... 3.2.3 EntryLo0 (2) and EntryLo1 (3) registers ...................................................................................... ...
Page 15
... BCURFCNTREG (0x0A00 0010) ................................................................................................ 115 6.2.5 REVIDREG (0x0A00 0014) ......................................................................................................... 116 6.2.6 CLKSPEEDREG (0x0A00 0018) ................................................................................................. 117 6.3 ROM Interface .......................................................................................................................... 118 6.3.1 External ROM devices memory mapping .................................................................................... 118 6.3.2 Connection to external ROM (x 16) devices ................................................................................ 119 6.3.3 Example of ROM connection ....................................................................................................... 120 6.3.4 External ROM cycles ................................................................................................................... 125 6.4 DRAM Interface ........................................................................................................................ 128 6.4.1 EDO DRAM configuration ............................................................................................................ 128 6 ...
Page 16
ISA Bridge Register Set ........................................................................................................... 137 6.7.1 ISABRGCTL (0x0B00 02C0) ....................................................................................................... 138 6.7.2 ISABRGSTS (0x0B00 02C2) ....................................................................................................... 139 6.7.3 XISACTL (0x0B00 02C4) ............................................................................................................. 140 CHAPTER 7 DMA CONTROL UNIT (DCU) ....................................................................................... 142 7.1 General ...................................................................................................................................... 142 7.2 DCU Registers ...
Page 17
SOFTINTREG (0x0A00 009A) .................................................................................................... 179 9.2.5 SYSINT2REG (0x0A00 0200) ..................................................................................................... 180 9.2.6 MSYSINT2REG (0x0A00 0206) .................................................................................................. 181 9.2.7 PIUINTREG (0x0B00 0082) ........................................................................................................ 182 9.2.8 AIUINTREG (0x0B00 0084) ........................................................................................................ 183 9.2.9 KIUINTREG (0x0B00 0086) ........................................................................................................ 184 9.2.10 MPIUINTREG (0x0B00 008E) ...
Page 18
CHAPTER 11 REALTIME CLOCK UNIT (RTC) ................................................................................ 216 11.1 General .................................................................................................................................... 216 11.2 Register Set ............................................................................................................................ 216 11.2.1 ElapsedTime registers ............................................................................................................... 217 11.2.2 ElapsedTime compare registers ................................................................................................ 219 11.2.3 RTCLong1 registers .................................................................................................................. 221 11.2.4 RTCLong1 count registers ......................................................................................................... 223 11.2.5 ...
Page 19
GPHIBSTH (0x0B00 0316) ...................................................................................................... 263 13.3.13 GPHIBSTL (0x0B00 0318) ...................................................................................................... 264 13.3.14 GPSICTL (0x0B00 031A) ........................................................................................................ 265 13.3.15 KEYEN (0x0B00 031C) ........................................................................................................... 267 13.3.16 PCS0STRA (0x0B00 0320) ..................................................................................................... 268 13.3.17 PCS0STPA (0x0B00 0322) ..................................................................................................... 268 13.3.18 PCS0HIA (0x0B00 0324) ...
Page 20
MCNTREG (0x0B00 0172) ........................................................................................................ 310 15.2.9 DVALIDREG (0x0B00 0178) ..................................................................................................... 311 15.2.10 SEQREG (0x0B00 017A) ........................................................................................................ 312 15.2.11 INTREG (0x0B00 017C) .......................................................................................................... 313 15.2.12 MCNVC_END (0x0B00 017E) ................................................................................................. 314 15.3 Operation Sequence ............................................................................................................. 315 15.3.1 Output (speaker) ........................................................................................................................ 315 ...
Page 21
SYSMEMSLnREG (Index: 0x10, 0x18, 0x20, 0x28, 0x30) ...................................................... 344 17.4.14 MEMWIDn_REG (Index: 0x11, 0x19, 0x21, 0x29, 0x31) ........................................................ 344 17.4.15 SYSMEMELnREG (Index: 0x12, 0x1A, 0x22, 0x2A, 0x32) ..................................................... 345 17.4.16 MEMSELn_REG (Index: 0x13, 0x1B, 0x23, 0x2B, 0x33) ........................................................ 345 ...
Page 22
CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2) ......................................................................... 379 20.1 General .................................................................................................................................... 379 20.2 Clock Control Logic ............................................................................................................... 379 20.3 Register Set ............................................................................................................................ 380 20.3.1 SIURB_2 (0x0C00 0000: LCR7 = 0, Read) ............................................................................... 381 20.3.2 SIUTH_2 (0x0C00 0000: LCR7 = ...
Page 23
FBSTADREG1 (0x0A00 0418) ................................................................................................ 422 21.4.14 FBSTADREG2 (0x0A00 041A) ................................................................................................ 422 21.4.15 FBENDADREG1 (0x0A00 0420) ............................................................................................. 423 21.4.16 FBENDADREG2 (0x0A00 0422) ............................................................................................. 423 21.4.17 FHSTARTREG (0x0A00 0424) ................................................................................................ 424 21.4.18 FHENDREG (0x0A00 0426) .................................................................................................... 424 21.4.19 PWRCONREG1 (0x0A00 0430) ...
Page 24
... CPU Instruction Formats (32-Bit Length Instruction) .................................................................................. 38 1-5. CPU Instruction Formats (16-Bit Length Instruction) .................................................................................. 39 1-6. Byte Address in Little-Endian Byte Order .................................................................................................... 41 1-7. Unaligned Word Accessing (Little Endian) .................................................................................................. 42 1-8. External Circuits of Clock Oscillator ............................................................................................................ 48 1-9. Incorrect Connection Circuits of Resonator ................................................................................................ 49 3-1. Index Register ............................................................................................................................................. 69 3-2. Random Register ........................................................................................................................................ 69 3-3. EntryLo0 and EntryLo1 Registers ............................................................................................................... 70 3-4. Context Register ......................................................................................................................................... 71 3-5. PageMask Register ..................................................................................................................................... 72 3-6 ...
Page 25
Fig. No. 5-1. RTC Reset .................................................................................................................................................. 97 5-2. RSTSW Reset ............................................................................................................................................. 98 5-3. Deadman’s Switch Reset ............................................................................................................................ 99 5-4. Software Shutdown ..................................................................................................................................... 100 5-5. HALTimer shutdown ................................................................................................................................... 101 5-6. V 4181 Activation Sequence (When Activation Is OK) ............................................................................... 102 R ...
Page 26
... Load Clock (LOCLK) ................................................................................................................................... 410 21-8. Frame Clock (FLM) ..................................................................................................................................... 410 21-9. LCD Timing Parameters .............................................................................................................................. 411 21-10. FLM Period .................................................................................................................................................. 411 22-1. Example of Connection of PLL Passive Components ................................................................................. 430 A-1. Mask Circuit for RSTSW# Signal ................................................................................................................ 436 A-2. Release of Self-Refresh Mode by RSTSW# Signal (EDO DRAM) .............................................................. 437 A-3. Release of Self-Refresh Mode by RSTSW# Signal (SDRAM) .................................................................... 438 26 ...
Page 27
Table No. 1-1. Supported PClock and TClock Frequencies ............................................................................................... 31 1-2. Devices Supported by System Bus ............................................................................................................. 31 1-3. GPIO(31:0) Pin Functions ........................................................................................................................... 33 1-4. LCD Panel Resolutions (in Pixels, TYP.) .................................................................................................... 34 1-5. Functions of LCD Interface Pins when ...
Page 28
Table No. 13-5. Serial Interface Channel 1 (SIU1) Loopback Control .................................................................................. 239 13-6. Serial Interface Channel 2 (SIU2) Signals .................................................................................................. 240 13-7. Serial Interface Channel 2 (SIU2) Loopback Control .................................................................................. 240 13-8. STN Color LCD Interface Signals ............................................................................................................... 241 13-9. ...
Page 29
... Supply voltage: 2.5 V for CPU core, 3.3 V for I/O • Package: 160-pin LQFP CHAPTER 1 INTRODUCTION 4181 ( µ PD30181), which is a 64-/32-bit microprocessor one of the V -Series microprocessor products manufactured by NEC R TM CPU core of ultra-low-power consumption with cache memory, high-speed User’s Manual U14272EJ3V0UM 29 ...
Page 30
Ordering Information Part number µ PD30181GM-66-8ED 1.3 V 4181 Key Features R EDO DRAM/ LCD Panel SDRAM LCD DCU controller 32.768 kHz V 4110 Clock R CPU core generator 18.432 MHz KIU LED RTC V 4181 R Keyboard LED ...
Page 31
... Bus interface The V 4181 incorporates single bus architecture. All external memory and I/O devices are connected to the same R 22-bit address bus and 16-bit data bus. These external address and data bus are together called the system bus. When the external bus operates at a very high speed, the DRAM data bus must be isolated from other low speed devices such as ROM array ...
Page 32
... The V 4181 provides an ExCA-compatible bus controller supporting a single CompactFlash slot. This interface is R shared with the keyboard interface logic and must be disabled when key matrix is connected to the V 1.3.10 Serial interface channel 1 (SIU1) The V 4181 provides a 16550 UART for implementing an RS-232-C type serial interface. When the serial R interface is not needed, each of the 7 serial interface pins can be individually redefined as general-purpose I/O pins ...
Page 33
Clocked serial interface (CSI) The V 4181 provides a clocked serial interface (CSI) which has an option to be configured as general-purpose I/O R pins. This interface supports slave mode operation only. The clocked serial interface requires allocation of ...
Page 34
... VPBIAS pins. Power sequencing is provided to prevent latch-up damage to the panel. The LCD controller can be disabled to allow connection of an external LCDC with integrated frame buffer RAM such as NEC Electronics’ µ PD16661. When the internal LCD controller is disabled, the SHCLK, LOCLK, VPLCD, and VPBIAS pins are redefined as follows: Table 1-5 ...
Page 35
Wake-up events The V 4181 supports 4 power management modes: Fullspeed, Standby, Suspend, and Hibernate. Of these R modes, Hibernate is the lowest power mode and results in the powering off of all system components including the 2.5 V ...
Page 36
CPU The CPU has hardware resources to process an integer instruction. They are the 64-bit register file, 64-bit integer data path, and multiply-and-accumulate operation unit. (2) Coprocessor 0 (CP0) The CP0 incorporates a memory management unit (MMU) and exception ...
Page 37
CPU registers The V 4110 core has thirty-two 64-bit general-purpose registers (GPRs addition, the processor provides the following special registers: • 64-bit Program Counter (PC) • 64-bit HI register, containing the integer multiply and divide upper doubleword ...
Page 38
CPU instruction set overview There are two types of CPU instructions: 32-bit length instructions (MIPS III) and 16-bit length instructions (MIPS16). Use of the MIPS16 instructions is enabled or disabled by setting MIPS16EN pin during a reset. For details ...
Page 39
MIPS16 instructions All the CPU instructions except for JAL and JALX are 16-bit length when executing MIPS16 instructions, and they are classified into thirteen instruction formats as shown in Figure 1-5. Figure 1-5. CPU Instruction Formats (16-Bit Length Instruction) ...
Page 40
The instruction set can be further divided into the following four groupings: (a) Load and store instructions move data between memory and general-purpose registers. They include RRI, RI, I8, and RI64 types. (b) Computational instructions perform arithmetic, logical, shift, and ...
Page 41
CHAPTER 1 INTRODUCTION Figure 1-6. Byte Address in Little-Endian Byte Order (a) Word data High-order 15 14 address Low-order 3 2 address (b) Doubleword data Word 63 High-order address ...
Page 42
The CPU core uses the following byte boundaries for halfword, word, and doubleword accesses: • Halfword: An even byte boundary (0, 2, 4...) • Word: A byte boundary divisible by four (0, 4, 8...) • Doubleword: A byte boundary divisible ...
Page 43
CP0 registers The CP0 has thirty-two registers, each of which has its own register number. Table 1-6 shows simple descriptions of each register. For the detailed descriptions of the registers, refer to CHAPTER 3 CP0 REGISTERS. Table 1-6. System ...
Page 44
... The V 4181 does not support the floating-point unit (FPU). Coprocessor Unusable exception will occur if any FPU R instructions are executed. If necessary, FPU instructions should be emulated by software in an exception handler. 1.4.6 Memory management unit The V 4181 has a 32-bit physical addressing range of 4 GB. However, since it is rare for systems to implement a ...
Page 45
Power modes The V 4181 supports four power modes: Fullspeed mode, Standby mode, Suspend mode, and Hibernate mode detailed description of these power modes is also given in CHAPTER 10 POWER MANAGEMENT UNIT (PMU). (1) Fullspeed mode ...
Page 46
... The V 4110 core is designed in consideration of the program compatibility to other V R However since it has some differences from other processors on their architecture, it cannot necessarily execute all programs that can be executed in other V necessarily execute all programs that can be executed in the V Matters that should be paid attention to when porting programs between the V processors are listed below. • ...
Page 47
Clock Interface The V 4181 has the following eight clocks. R • CLKX1, CLKX2 (input) These are oscillation inputs of 18.432 MHz, and used to generate operation clocks for the CPU core, serial interface, and other peripheral units. • ...
Page 48
... Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. Ensure that no load such as wiring capacity is applied to the CLKX2 or RTCX2 pin when inputting an external clock. Figure 1-9 shows examples of the incorrect connection circuit of the resonator. 48 CHAPTER 1 INTRODUCTION V 4181 ...
Page 49
... Figure 1-9. Incorrect Connection Circuits of Resonator (a) Connection circuit wiring is too long. Note 1 Note 2 Note 3 (c) A high fluctuating current flows near a signal line. Note 1 Note 2 Note 3 Large current (e) A signal is fetched. Note 2 Note 1 Note 3 CHAPTER 1 INTRODUCTION (b) There is another signal line crossing. Note 1 (d) A current flows over the ground line of the oscillator (The potentials of points A, B, and C change) ...
Page 50
Pin Configuration • 160-pin plastic LQFP (fine pitch) (24 × 24) GND_AD 1 GND_TP 2 TPX0 3 TPX1 4 TPY0 5 TPY1 6 VDD_TP 7 ADIN0 8 ADIN1 9 ADIN2 10 AUDIOIN 11 VDD_AD 12 AUDIOOUT 13 IORDY/GPIO18 14 ...
Page 51
Pin Identification ADD(21:0) : Address Bus ADIN(2:0) : Analog Data Input AUDIOIN : Audio Input AUDIOOUT : Audio Output BATTINH : Battery Inhibit BATTINT# : Battery Interrupt CAS# : Column Address Strobe CD1#, CD2# : Card Detect for CompactFlash CF_AEN# ...
Page 52
Pin Function Description Remark # indicates active low. 2.2.1 System bus interface signals Signal name I/O Note ADD(21:0) Output DATA(15:0) I/O IORD#/GPIO16 I/O IOWR#/GPIO17 I/O IORDY/GPIO18 I/O IOCS16#/GPIO19 I/O UBE#/GPIO20/M I/O RESET#/GPIO21 I/O Note The V 4181 utilizes different ...
Page 53
... SDRAM chip select for bank 0 and bank 1 or EDO DRAM row address strobes. SDRAM column address strobe. Leave unconnected when using EDO DRAM. SDRAM row address strobe. Leave unconnected when using EDO DRAM. SDRAM upper byte enable or EDO DRAM upper byte column address strobe. ...
Page 54
... SHCLK/LCDCS# Output LOCLK/MEMCS16# I/O FLM/MIPS16EN I/O Note FPD(7:4)/GPIO(15:12) Output Note FPD(3:0) Output VPLCD/VPGPIO1 Output VPBIAS/VPGPIO0 Output Note Connection between FPD(7:0) of the V width as below. For details, refer to CHAPTER 21 LCD CONTROLLER. V 4181 R FPD0 FPD1 FPD2 FPD3 FPD4 FPD5 FPD6 FPD7 54 CHAPTER 2 PIN FUNCTIONS Description of function LCD shift clock output or chip select for external LCD controller ...
Page 55
... This is an interrupt signal that is input when remaining battery power is low during normal operations. The external agent checks the remaining battery power and activates this signal if voltage sufficient for operations cannot be supplied. Description of function Connections to 32.768 kHz crystal resonator. Connections to 18.432 MHz crystal resonator. User’s Manual U14272EJ3V0UM 55 ...
Page 56
Touch panel interface and audio interface signals Signal name I/O TPX(1:0) I/O TPY(1:0) I/O ADIN(2:0) Input AUDIOIN Input AUDIOOUT Output 2.2.7 LED interface signals Signal name I/O LEDOUT Output 2.2.8 CompactFlash interface and keyboard interface signals Signal name I/O ...
Page 57
Serial interface channel 1 signals Signal name I/O RxD1/GPIO25 I/O TxD1/GPIO26/CLKSEL0 I/O RTS1#/GPIO27/CLKSEL1 I/O CTS1#/GPIO28 I/O DCD1#/GPIO29 I/O DTR1#/GPIO30/CLKSEL2 I/O DSR1#/GPIO31 I/O Note CLKSEL(2:0) signals are used to set the frequency of the CPU core operation clock (PClock). These ...
Page 58
... CHAPTER 2 PIN FUNCTIONS Description of function IrDA receive data input or serial channel 2 receive data input. Connect this pin to GND (digital) via resistor when an IrDA receive component is connected. IrDA transmit data output or serial channel 2 transmit data output. Description of function See 2.2.9 Serial interface channel 1 signals in this section See 2 ...
Page 59
Dedicated V /GND signals DD Signal name Power supply VDD_PLL 2.5 V GND_PLL 2.5 V VDD_TP 3.3 V GND_TP 3.3 V VDD_AD 3.3 V GND_AD 3.3 V VDD_OSC 3.3 V GND_OSC 3.3 V VDD_LOGIC 2.5 V GND_LOGIC 2.5 V ...
Page 60
Pin Status in Specific Status Signal Name During RTC Reset ADD(21:0) Hi-Z DATA(15:0) Hi-Z MEMRD# Hi-Z MEMWR# Hi-Z SDCS(1:0)#/RAS(1:0)# Hi-Z UDQM/UCAS# Hi-Z LDQM/LCAS# Hi-Z CAS# Hi-Z SDRAS# Hi-Z SDCLK Hi-Z CLKEN Hi-Z SYSDIR Hi-Z SYSEN# Hi-Z IORD#/GPIO16 IOWR#/GPIO17 IORDY/GPIO18 ...
Page 61
Signal Name During RTC Reset POWERON MPOWER BATTINH/BATTINT# RTCX2, RTCX1 CLKX2, CLKX1 TPX(1:0) TPY(1:0) ADIN(2:0) AUDIOIN AUDIOOUT CF_WE#/SCANOUT7 Hi-Z CF_OE#/SCANOUT6 Hi-Z CF_IOW#/SCANOUT5 Hi-Z CF_IOR#/SCANOUT4 Hi-Z CF_STSCHG#/SCANOUT3 Hi-Z CF_CE(2:1)#/ Hi-Z SCANOUT(2:1) CF_BUSY#/SCANOUT0 Hi-Z CF_REG#/SCANIN7 Hi-Z CF_RESET/SCANIN6 Hi-Z CF_WAIT#/SCANIN5 CF_IOIS16#/SCANIN4 CF_VCCEN#/SCANIN3 Hi-Z ...
Page 62
Signal Name During RTC Reset RxD1/GPIO25 TxD1/GPIO26/CLKSEL0 Note 3 RTS1#/GPIO27/CLKSEL1 Note 3 CTS1#/GPIO28 DCD1#/GPIO29 DTR1#/GPIO30/CLKSEL2 Note 3 DSR1#/GPIO31 IRDIN/RxD2 IRDOUT/TxD2 Hi-Z GPIO(15:14)/FPD(7:6)/ CD(2:1)# GPIO(13:12)/FPD(5:4) − /Hi-Z GPIO11/PCS1# − /Hi-Z GPIO10/FRM/SYSCLK GPIO9/CTS2# GPIO8/DSR2# GPIO7/DTR2# GPIO6/RTS2# GPIO5/DCD2# GPIO4 − /Hi-Z GPIO3/PCS0# GPIO2/SCK ...
Page 63
... VPLCD/VPGPIO1 VPBIAS/VPGPIO0 POWER RTCRST# RSTSW# POWERON MPOWER BATTINH/BATTINT# TPX(1:0) TPY(1:0) Remark No specification (−) in the Recommended Connection When Not Used column indicates that the pin is always connected. CHAPTER 2 PIN FUNCTIONS Recommended Connection When Not Used − − − − − − − ...
Page 64
... Connect to VDD_IO or GND_IO via resistor Leave open Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor ...
Page 65
... GPIO2/SCK GPIO1/SO GPIO0/SI LEDOUT CHAPTER 2 PIN FUNCTIONS Recommended Connection When Not Used Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Leave open User’s Manual U14272EJ3V0UM (3/3) I/O Circuit Type ...
Page 66
Pin I/O Circuits Type A Data Output disable Input enable Type B Data Output disable P-ch + − N-ch V ref 66 CHAPTER 2 PIN FUNCTIONS Type Data P-ch IN/OUT Output N-ch disable + − V ...
Page 67
Coprocessor 0 (CP0) The Coprocessor 0 (CP0), which is also called as System Control Coprocessor, is implemented as an integral part of the CPU, and supports memory management, address translation, exception handling, and operation mode control. Memory management, address ...
Page 68
Number Register 0 Index Memory management 1 Random Memory management 2 EntryLo0 Memory management 3 EntryLo1 Memory management 4 Context Exception processing 5 PageMask Memory management 6 Wired Memory management − BadVAddr Exception processing 9 Count Exception processing ...
Page 69
Details of CP0 Registers 3.2.1 Index register (0) The Index register is a 32-bit, read/write register containing five low-order bits to index an entry in the TLB. The most-significant bit of the register shows the success or failure of ...
Page 70
EntryLo0 (2) and EntryLo1 (3) registers The EntryLo register consists of two registers that have identical formats: EntryLo0, used for even virtual pages and EntryLo1, used for odd virtual pages. The EntryLo0 and EntryLo1 registers are both read-/write-accessible. They ...
Page 71
C bit value 3.2.4 Context register (4) The Context register is a read/write register containing the pointer to an entry in the page table entry (PTE) array on the memory; this array ...
Page 72
PageMask register (5) The PageMask register is a read/write register used for reading from or writing to the TLB; it holds a comparison mask that sets the page size for each TLB entry, as shown in Table 3-3. Five ...
Page 73
Wired register (6) The Wired register is a read/write register that specifies the lower boundary of the random entry of the TLB as shown in Figure 3-6. Wired entries cannot be overwritten by a TLBWR instruction, but by a ...
Page 74
BadVAddr register (8) The Bad Virtual Address (BadVAddr) register is a read-only register that saves the most recent virtual address that failed to have a valid translation, or that had an addressing error. Caution This register saves no information ...
Page 75
EntryHi register (10) The EntryHi register is write-accessible used to access the built-in TLB. The EntryHi register holds the high- order bits of a TLB entry for TLB read and write operations TLB Refill, TLB ...
Page 76
... CHAPTER 3 CP0 REGISTERS Figure 3-11. Compare Register Compare Figure 3-12. Status Register (1/ 4181 supports the little-endian order only. R Note ). However, Int(4:3) 4110 CPU core. For details about connection to R User’s Manual U14272EJ3V0UM KSU ERL ...
Page 77
Enables 64-bit addressing in Kernel mode (0 → 32-bit, 1 → 64-bit). 64-bit operations are always KX: valid in Kernel mode. Enables 64-bit addressing and operation in Supervisor mode (0 → 32-bit, 1 → 64-bit). SX: Enables 64-bit addressing and ...
Page 78
Interrupt enable Interrupts are enabled when all of the following conditions are true: • IE bit is set to 1. • EXL bit is cleared to 0. • ERL bit is cleared to 0. • The appropriate bit of ...
Page 79
... Reserved for future use. Write write operation. When this field is read read. CHAPTER 3 CP0 REGISTERS Figure 3-14. Cause Register IP(7:0) 0 Note Note ). However, Int(4:3) 4110 CPU core. For details about connection to R User’s Manual U14272EJ3V0UM ExcCode 0 never occurs in the V 4181. R ...
Page 80
Table 3-4. Cause Register Exception Code Field Exception code The V 4181 has eight interrupt request sources, IP7 to ...
Page 81
Exception Program Counter (EPC) register (14) The Exception Program Counter (EPC read/write register that contains the address at which processing resumes after an exception has been serviced. execution of MIPS16 instructions is enabled or disabled. Setting the ...
Page 82
... The processor revision number can distinguish CPU core revisions of the V that changes to the CPU core will necessarily be reflected in the PRId register, or that changes to the revision number necessarily reflect real CPU core changes. Therefore, create a program that does not depend on the processor revision number field ...
Page 83
Config register (16) The Config register specifies various configuration options selected on the V Some configuration options, as defined by the EC and BE fields, are set by the hardware during Cold Reset and are included in the Config ...
Page 84
K0: kseg0 cache coherency algorithm 2 → Uncached Others → Cached returned when read returned when read. 3.2.16 Load Linked Address (LLAddr) register (17) The read/write Load Linked Address (LLAddr) register is not used ...
Page 85
WatchLo (18) and WatchHi (19) registers The V 4181 processor provides a debugging feature to detect references to a selected physical address; load and R store instructions to the location specified by the WatchLo and WatchHi registers cause a ...
Page 86
XContext register (20) The read/write XContext register contains a pointer to an entry in the page table entry (PTE) array, an operating system data structure that stores virtual-to-physical address translations TLB miss occurs, the operating system loads ...
Page 87
Parity Error register (26) The Parity Error (PErr) register is a readable/writable register. This register is defined to maintain software- compatibility with the V 4100, and is not used in hardware because the Diagnostic:8-bit self diagnostic ...
Page 88
TagLo (28) and TagHi (29) registers The TagLo and TagHi registers are 32-bit read/write registers that hold the primary cache tag during cache initialization, cache diagnostics, or cache error processing. The Tag registers are written by the CACHE and ...
Page 89
ErrorEPC register (30) The Error Exception Program Counter (ErrorEPC) register is similar to the EPC register used to store the Program Counter value at which the Cold Reset, Soft Reset, or NMI exception has been serviced. The ...
Page 90
Figure 3-27. ErrorEPC Register (When MIPS16 ISA Is Disabled ErrorEPC: Virtual restart address after Cold reset, Soft reset, or NMI exception. Figure 3-28. ErrorEPC Register (When MIPS16 ISA Is Enabled) 31 ErrorEPC: Bits virtual ...
Page 91
CHAPTER 4 MEMORY MANAGEMENT SYSTEM 4.1 Overview The V 4181 provides a memory management unit (MMU) which uses a translation lookaside buffer (TLB translate virtual addresses into physical addresses. Virtual addresses are translated into physical addresses using an ...
Page 92
CHAPTER 4 MEMORY MANAGEMENT SYSTEM 4.2 Physical Address Space Using a 32-bit address, the processor physical address space encompasses 4 GB. The V physical address space as shown in Figure 4-1. Figure 4-1. V 0xFFFF FFFF 0x2000 0000 0x1FFF FFFF ...
Page 93
CHAPTER 4 MEMORY MANAGEMENT SYSTEM Table 4-1. V Physical address 0xFFFF FFFF to 0x2000 0000 0x1FFF FFFF to 0x1800 0000 0x17FF FFFF to 0x1400 0000 0x13FF FFFF to 0x1000 0000 0x0FFF FFFF to 0x0D00 0000 0x0CFF FFFF to 0x0C00 0000 ...
Page 94
CHAPTER 4 MEMORY MANAGEMENT SYSTEM 4.2.3 Internal I/O space The V 4181 has three internal I/O spaces. Each of these spaces is described below. R Physical address 0x0C00 001F to 0x0C00 0010 0x0C00 000F to 0x0C00 0000 Physical address 0x0B00 ...
Page 95
CHAPTER 4 MEMORY MANAGEMENT SYSTEM Physical address 0x0A00 06FF to 0x0A00 0600 0x0A00 05FF to 0x0A00 0500 0x0A00 04FF to 0x0A00 0400 0x0A00 03FF to 0x0A00 0300 0x0A00 02FF to 0x0A00 0220 0x0A00 021F to 0x0A00 0200 0x0A00 01FF to ...
Page 96
CHAPTER 5 INITIALIZATION INTERFACE This chapter describes the reset signal descriptions and types, signal- and timing-related dependence, and the initialization sequence during each mode that can be selected by the user. A detailed description of the operation during and after ...
Page 97
RTC reset During power-on, set the RTCRST# pin as active. After waiting about 600 ms for the 32.768 kHz oscillator to begin oscillating when the power supply is stable at 3 above, setting the RTCRST# pin as ...
Page 98
RSTSW reset After the RSTSW# pin becomes active and then becomes inactive 100 µ s later, the V and starts all clocks (a period of about 16 ms following the start of PLL oscillation is required for stabilization of ...
Page 99
Deadman’s Switch reset After the Deadman’s Switch unit is enabled, if the Deadman’s Switch is not cleared within the specified time period, the V 4181 immediately enters to reset status. Setting and clearing of the Deadman’s Switch is performed ...
Page 100
Software shutdown When the software executes the HIBERNATE instruction, the V enters reset status. Recovery from reset status occurs when the POWER pin or DCD# signal is asserted or when an unmasked wake-up interrupt request is occurred. A reset ...
Page 101
HALTimer shutdown After an RTC reset or RSTSW reset is canceled, if the HALTimer is not canceled (the HALTIMERRST bit of the PMUCNTREG register is not set) by software within about four seconds, the V from reset status occurs ...
Page 102
Power-on Sequence The factors that cause the V 4181 to switch from Hibernate mode or shutdown mode to Fullspeed mode are R called activation factors. There are five activation factors: assertion of the POWER pin, the DCD1# pin or ...
Page 103
CHAPTER 5 INITIALIZATION INTERFACE Figure 5-7. V 4181 Activation Sequence (When Activation Is NG) R POWERON (Output) L MPOW ER (Output) ColdReset# (Internal) L Reset# (Internal) L BATTINH/BATTINT# (Input) PLL (Internal) H RTC (Internal, 32.768 kHz) Detection of activation factor ...
Page 104
Reset of CPU Core This section describes the reset sequence of the V 5.3.1 Cold Reset In the V 4181, a Cold Reset sequence is executed in the CPU core in the following cases: R • RTC reset • ...
Page 105
Soft Reset Caution Soft Reset is not supported in the current V A Soft Reset initializes the CPU core without affecting the output clocks; in other words, a Soft Reset is a logical reset Soft Reset, the ...
Page 106
... The clock is not supplied in the default status to the peripheral units such as CSI, AIU, PIU, SIU1, and SIU2, and the A/D and D/A converters. To start using these units and converters, supply the necessary clock to them by setting the CMUCLKMSK register in the MBA Host Bridge. If these units are not used or they have finished being used, mask the clock supply by setting the CMUCLKMSK register ...
Page 107
Returning from power mode For initialization after the V 4181 has returned from the Hibernate mode or Suspend mode, refer to 10.6 DRAM R Interface Control. CHAPTER 5 INITIALIZATION INTERFACE User’s Manual U14272EJ3V0UM 107 ...
Page 108
MBA Host Bridge The MBA (Modular Bus Architecture) Host Bridge is an interface between the CPU core and the MBA bus and operates as an external agent to the CPU core. It handles all requests from the CPU core ...
Page 109
MBA Host Bridge ROM and register address space Physical address 0x1FFF FFFF to 0x1800 0000 0x0A00 0014 to 0x0A00 0000 0x0A00 0080 0x0A00 008C 0x0A00 0098 0x0A00 009A 0x0A00 0200 0x0A00 0206 In addition to the decoding of above ...
Page 110
ISA Bridge Physical address 0x17FF FFFF to 0x1400 0000 0x13FF FFFF to 0x1000 0000 0x0BFF FFFF to 0x0B00 0000 0x0CFF FFFF to 0x0C00 0000 The ISA Bridge is selected when the above address ranges are accessed. 6.2 Bus Control ...
Page 111
BCUCNTREG1 (0x0A00 0000) Bit 15 14 Name ROMs1 ROMs0 R/W R/W R/W At reset 1 0 Bit 7 6 Name Reserved Reserved R reset 0 0 Bit Name 15, 14 ROMs(1: Reserved 4 ...
Page 112
CMUCLKMSK (0x0A00 0004) Bit 15 14 Name Reserved Reserved R reset 0 0 Bit 7 6 Name Reserved MSKCSU PCLK R/W R R/W At reset 0 0 Bit Name Reserved 6 MSKCSUPCLK 5 ...
Page 113
BCUSPEEDREG (0x0A00 000C) Bit 15 14 Name Reserved WPROM2 R/W R R/W At reset 0 1 Bit 7 6 Name Reserved Reserved R reset 0 0 Bit Name 15 Reserved WPROM(2: ...
Page 114
Figure 6-2. ROM Read Cycle and Access Parameters TClock (internal) ADD(21:0) (output) ROMCS(3:0)# (output) MEMRD# (output) DATA(15:0) (read) TClock (internal) ADD(21:3) (output) ADD(2:0) (output) ROMCS(3:0)# (output) DATA(15:0) (read) Remarks 1. ROMCS(2:0)# signals are alternated with general-purpose I/O signals and are ...
Page 115
BCURFCNTREG (0x0A00 0010) Bit 15 14 Name Reserved Reserved R reset 0 0 Bit 7 6 Name BRF7 BRF6 R/W R/W R/W At reset 1 1 Bit Name 15, 14 Reserved BRF(13:0) Remarks ...
Page 116
... Even if the CPU core or the peripheral unit has been changed, there is no guarantee that REVIDREG register will be reflected, or that the changes to the revision number necessarily reflect real changes of the CPU core or the peripheral unit. For this reason, software should not rely on the revision number in REVIDREG register to characterize the units ...
Page 117
CLKSPEEDREG (0x0A00 0018) Bit 15 14 Name DIV2 DIV3 R Bit 7 6 Name Reserved Reserved R Bit Name DIV(2: Reserved CLKSP(4:0) The following expression is ...
Page 118
ROM Interface The V 4181 supports three ROM modes, ordinary ROM, PageROM, and flash memory. The mode setting is made R via the BCUCNTREG1 register’s Rtype(1:0) bits and ROMWEN0 bit. Access speed setting in ordinary ROM or PageROM mode ...
Page 119
... Connection to external ROM (x 16) devices The ADD(21:0) pins are connected to the address line ADD(21:0) inside the V However, during ROM or flash memory accesses, they are connected to the address line ADD(22:1) inside the V 4181. This allows providing a greater address space capacity for ROM or flash memory. ...
Page 120
... Example of ROM connection (1) 32 Mbit ordinary ROM ADD(20:0) A(20:0) ROMCS0# ROMCS1# ROM Bank0 D(15:0) DATA(15:0) (2) 64 Mbit ordinary ROM ADD(21:0) A(21:0) ROMCS0# ROMCS1# ROM Bank0 D(15:0) DATA(15:0) 120 CHAPTER 6 BUS CONTROL A(20:0) A(20:0) ROMCS2# ROM ROM Bank1 Bank2 D(15:0) D(15:0) A(21:0) A(21:0) ROMCS2# ROM ROM Bank1 Bank2 D(15:0) D(15:0) User’s Manual U14272EJ3V0UM ...
Page 121
Mbit PageROM Remark The maximum burst number when using a PageROM is 8 halfwords (i.e. 128 bits; 1 word = 32 bits). ADD(20:3) ADD(2:0) A(19:2) A(1:−1) Page ROM Bank0 ROMCS0# ROMCS1# CE DW/W# D(15:0) DATA(15:0) CHAPTER 6 BUS ...
Page 122
Mbit PageROM Remark The maximum burst number when using a PageROM is 8 halfwords (i.e. 128 bits; 1 word = 32 bits). ADD(21:3) ADD(2:0) A(20:2) A(1:−1) Page ROM Bank0 ROMCS0# ROMCS1# CE DW/W# D(15:0) DATA(15:0) 122 CHAPTER 6 ...
Page 123
Mbit flash memory (when using Intel ADD(19:0) ADD20 A(20:1) CE2 CE1 Flash memory Bank0 Flash Note Ready RDY/BSY# ROMCS0# ROMCS1# CE0 MEMWR# WE MEMRD# OE D(15:0) DATA(15:0) Note There is no corresponding pin in the V Remark Use ...
Page 124
Mbit flash memory (when using Intel StrataFlash ADD(21:0) A(21:0) CE2 CE1 Flash memory Bank0 Flash Note Status STS ROMCS0# ROMCS1# CE0 MEMWR# WE MEMRD# OE D(15:0) DATA(15:0) Note There is no corresponding pin in the V Remark Using ...
Page 125
External ROM cycles The following timing diagrams illustrate the external ROM cycles depending on the settings in the bus control register and bus speed control register. (1) Ordinary ROM read cycle Figure 6-3. Ordinary ROM Read Cycle (WROMA(3:0) = ...
Page 126
PageROM read cycle Figure 6-4. PageROM Read Cycle (WROMA(3:0) = 0011, WPROM(2:0) = 001) TClock (internal) ADD(21:0) Adr0 (output) ROMCS(3:0)# (output) MEMRD# L (output) WROMA(3:0) WPROM(2:0) DATA(15:0) Data0 (read) Remark A circle in the figure indicates the sampling timing. ...
Page 127
Flash memory read cycle Figure 6-5. Flash Memory Read Cycle (Rtype(1:0) = 01, WROMA(3:0) = 0101) TClock (internal) ADD(21:0) (output) ROMCS(3:0)# (output) MEMRD# (output) DATA(15:0) (read) Remark A circle in the figure indicates the sampling timing. (4) Flash memory ...
Page 128
... RAS0# DATA(15:0) V 4181 R RAS1# Figure 6-7 illustrates an example when connecting devices of 4 Mbits x 16. Addresses when connecting devices of 16 Mbits or 64 Mbits are mapped as follows. DRAM bank Bank 0 0x001F FFFF to 0x0000 0000 Bank 1 0x003F FFFF to 0x0020 0000 Remark 64 Mbit EDO DRAMs of other than 13 rows and 9 columns cannot be used with the V ...
Page 129
Mixed memory mode (EDO DRAM only) The MEMCFG_REG register provides two bits each for Bank 0 and Bank 1 to set types of DRAMs to be used. This allows the two banks to be configured with different types of ...
Page 130
... UDQM LDQM MEMWR# SDCS0# DATA(15:0) SDCLK CLKEN V 4181 R SDCS1# Figure 6-8 illustrates an example when connecting devices of 4 Mbits x 16. Remark The SDRAMs supported by the V Capacity 16 Mbits 512 Kbits banks 64 Mbits 2 Mbits banks 64 Mbits 1 Mbits banks 130 CHAPTER 6 BUS CONTROL Figure 6-8 ...
Page 131
Memory Controller Register Set Physical address R/W 0x0A00 0300 R/W EDOMCYTREG 0x0A00 0304 R/W MEMCFG_REG 0x0A00 0308 R/W MODE_REG 0x0A00 030C R/W SDTIMINGREG Caution Since these registers are powered by 2.5 V power supply, the contents of these registers ...
Page 132
Bit Name 5, 4 Tcas(1: Trp(1: Tras(1:0) This register is used to set EDO DRAM timing parameters. Software must set these parameters suitable before using DRAM. Remark Do not set Tcas = 1/2 TClock and Caspre ...
Page 133
MEMCFG_REG (0x0A00 0304) Bit 15 14 Name Init Reserved R/W R reset 0 0 Bit 7 6 Name BstRefr EDOAsym R/W R/W R/W At reset 0 0 Bit Name 15 Init Reserved 11, 10 ...
Page 134
Bit Name Reserved 2, 1 B0Config(1:0) 0 EDO/SDRAM This register is used to set DRAM type (capacity, type, organization, etc.) of Bank 0 and Bank 1. Caution When using SDRAMs, set the Init bit ...
Page 135
MODE_REG (0x0A00 0308) Bit 15 14 Name Reserved Reserved R reset 0 0 Bit 7 6 Name TE-Ven2 LTMode2 R/W R/W R/W At reset 0 0 Bit Name Reserved 11 ...
Page 136
SDTIMINGREG (0x0A00 030C) Bit 15 14 Name Reserved Reserved R reset 0 0 Bit 7 6 Name TRAS1 TRAS0 R/W R/W R/W At reset 0 0 Bit Name Reserved 9 Reserved 8 Reserved ...
Page 137
ISA Bridge The V 4181 has an external bus used for ROM, flash memory, DRAM, and I/O. This bus’s operation emulates an R ISA bus at accesses to external memory and I/O spaces. The V embedded peripherals. Among the ...
Page 138
ISABRGCTL (0x0B00 02C0) Bit 15 14 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit Name 15 to ...
Page 139
ISABRGSTS (0x0B00 02C2) Bit 15 14 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit Name 15 to ...
Page 140
XISACTL (0x0B00 02C4) Bit 15 14 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name MEMWS1 MEMWS0 R/W R/W R/W RTCRST 0 0 Other resets 0 0 Bit Name 15 to ...
Page 141
Bit Name 3, 2 Reserved 1, 0 SCLKDIV(1:0) This register is used to set the external ISA configurations. SYSCLK is an operation clock for the external ISA bus, and is output only when an external ISA cycle is generated. CHAPTER ...
Page 142
CHAPTER 7 DMA CONTROL UNIT (DCU) 7.1 General The DMA Control Unit (DCU) controls four channels of DMA transfer. Two of them are allocated for the AIU (microphone and speaker), though the remaining two are reserved for future use. The ...
Page 143
CHAPTER 7 DMA CONTROL UNIT (DCU) Priority of each DMA channel is fixed. The channel priority is as follows. 1. AIU Microphone channel 2. AIU Speaker channel DCU runs at the MBA bus clock (TClock) frequency. Remark The DCU contains ...
Page 144
DCU Registers Physical address R/W 0x0A00 0020 R/W MICDEST1REG1 0x0A00 0022 R/W MICDEST1REG2 0x0A00 0024 R/W MICDEST2REG1 0x0A00 0026 R/W MICDEST2REG2 0x0A00 0028 R/W SPKRSRC1REG1 0x0A00 002A R/W SPKRSRC1REG2 0x0A00 002C R/W SPKRSRC2REG1 0x0A00 002E R/W SPKRSRC2REG2 0x0A00 0040 ...
Page 145
Microphone destination 1 address registers (1) MICDEST1REG1 (0x0A00 0020) Bit 15 14 Name MD1A15 MD1A14 R/W R/W R/W At reset 0 0 Bit 7 6 Name MD1A7 MD1A6 R/W R/W R/W At reset 0 0 Bit Name 15 to ...
Page 146
Microphone destination 2 address registers (1) MICDEST2REG1 (0x0A00 0024) Bit 15 14 Name MD2A15 MD2A14 R/W R/W R/W At reset 0 0 Bit 7 6 Name MD2A7 MD2A6 R/W R/W R/W At reset 0 0 Bit Name 15 to ...
Page 147
Speaker source 1 address registers (1) SPKRSRC1REG1 (0x0A00 0028) Bit 15 14 Name SS1A15 SS1A14 R/W R/W R/W At reset 0 0 Bit 7 6 Name SS1A7 SS1A6 R/W R/W R/W At reset 0 0 Bit Name 15 to ...
Page 148
Speaker source 2 address registers (1) SPKRSRC2REG1 (0x0A00 002C) Bit 15 14 Name SS2A15 SS2A14 R/W R/W R/W At reset 0 0 Bit 7 6 Name SS2A7 SS2A6 R/W R/W R/W At reset 0 0 Bit Name 15 to ...
Page 149
DMARSTREG (0x0A00 0040) Bit 15 14 Name Reserved Reserved R reset 0 0 Bit 7 6 Name Reserved Reserved R reset 0 0 Bit Name Reserved 0 DMARST When DMARST ...
Page 150
MICRCLENREG (0x0A00 0658) Bit 15 14 Name MICRL15 MICRL14 R/W R/W R/W At reset 1 1 Bit 7 6 Name MICRL7 MICRL6 R/W R/W R/W At reset 1 1 Bit Name MICRL(15:0) This register defines the ...
Page 151
MICDMACFGREG (0x0A00 065E) Bit 15 14 Name Reserved MicDsize1 R reset 0 0 Bit 7 6 Name Reserved Reserved R reset 0 0 Bit Name 15 Reserved 14, 13 MicDsize(1:0) 12 MicSrctype 11 ...
Page 152
SPKDMACFGREG (0x0A00 0660) Bit 15 14 Name Reserved Reserved R reset 0 0 Bit 7 6 Name Reserved SpkDsize1 R reset 0 0 Bit Name Reserved 6, 5 SpkDsize(1:0) 4 ...
Page 153
DMAITRQREG (0x0A00 0662) Bit 15 14 Name Reserved Reserved R reset 0 0 Bit 7 6 Name Reserved Reserved R reset 0 0 Bit Name Reserved 5 SpkEOP 4 MicEOP ...
Page 154
DMACTLREG (0x0A00 0664) Bit 15 14 Name SpkCNT1 SpkCNT0 R/W R/W R/W At reset 0 0 Bit 7 6 Name Reserved Reserved R/W R/W R/W At reset 0 0 Bit Name 15, 14 SpkCNT(1:0) 13, 12 MicCNT(1: ...
Page 155
DMAITMKREG (0x0A00 0666) Bit 15 14 Name Reserved Reserved R reset 0 0 Bit 7 6 Name Reserved Reserved R reset 0 0 Bit Name Reserved 5 SpkEOPMsk 4 MicEOPMsk ...
Page 156
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.1 Overview The CSI manages communication via a synchronous serial bus. The CSI of the V characteristics: • Slave-only synchronous serial interface • Able to transmit and receive data simultaneously • Supports fixed ...
Page 157
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.2.2 SCK phase and CSI transfer timing The external master drives SCK and SI and samples data driven on SO. The CSI supports 4 basic operating modes of SCK depending on the settings ...
Page 158
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) The four modes of SCK are described below. (1) When CKMD bit = 0 and CKPOL bit = 0 • Transmission The first transmit data bit is output before the first rising edge ...
Page 159
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.2.3 CSI transfer types (1) Burst mode Burst mode is supported for both transmit and receive transfers. Burst lengths for transmission and reception are independently programmable and can be set from 1 to ...
Page 160
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.2.4 Transmit and receive FIFOs The CSI contains two 8-deep 16-bit FIFOs. One is for transmission and the other for reception. The transmit and receive shift registers access the FIFOs by 8 bits ...
Page 161
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.3.1 CSIMODE (0x0B00 0900) Bit 15 14 Name FRMEN TXEN R/W R/W R/W RTCRST 0 0 Other resets 0 0 Bit 7 6 Name FRMMD CKPOL R/W R/W R/W RTCRST 0 0 Other ...
Page 162
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) Bit Name 7 FRMMD 6 CKPOL 5 CKMD Reserved 0 LSBMSB Note The TXCLR and RXCLR bits must be cleared after changing the CKPOL or CKMD bit. The CKPOL bit ...
Page 163
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.3.2 CSIRXDATA (0x0B00 0902) Bit 15 14 Name RXD15 RXD14 R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name RXD7 RXD6 R RTCRST 0 0 Other ...
Page 164
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.3.4 CSILSTAT (0x0B00 0906) Bit 15 14 Name TFIFOT1 TFIFOT0 R/W R/W R/W RTCRST 0 0 Other resets 0 0 Bit 7 6 Name RFIFOT1 RFIFOT0 R/W R/W R/W RTCRST 0 0 Other ...
Page 165
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) Bit Name 4 FRMDIR 3 Reserved 2 RXFIFOF 1 RXFIFOE 0 RXBUSY Function FRM input pin status 0 : Low level (transmit direction High level (receive direction returned after ...
Page 166
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.3.5 CSIINTMSK (0x0B00 0908) Bit 15 14 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name Reserved Reserved R RTCRST 0 0 Other ...
Page 167
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.3.6 CSIINTSTAT (0x0B00 090A) Bit 15 14 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name Reserved Reserved R RTCRST 0 0 Other ...
Page 168
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) Bit Name 2 RXBEINT 1 RXFFINT 0 RXBSYINT 168 Function Receive Burst End interrupt request status 0 : Not pending 1 : Pending This bit is cleared by writing 1. Receive FIFO Full ...
Page 169
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.3.7 CSITXBLEN (0x0B00 090C) Bit 15 14 Name TXBLN15 TXBLN14 R/W R/W R/W RTCRST 0 0 Other resets 0 0 Bit 7 6 Name TXBLN7 TXBLN6 R/W R/W R/W RTCRST 0 0 Other ...
Page 170
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.3.8 CSIRXBLEN (0x0B00 090E) Bit 15 14 Name RXBLN15 RXBLN14 R/W R/W R/W RTCRST 0 0 Other resets 0 0 Bit 7 6 Name RXBLN7 RXBLN6 R/W R/W R/W RTCRST 0 0 Other ...
Page 171
... MSYSINTREG, a corresponding interrupt request signal is output from the ICU to the CPU core. battintr is connected to the NMI or Int0 signal of the CPU core (selected by setting of NMIREG). rtclong2 and rtclong1 signals are connected to the Int2 or Int1 signal of the CPU core. The other interrupt requests are connected to the Int0 signal of the CPU core as a single interrupt request ...
Page 172
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) Level 2 registers and signals from peripheral units dozepiuint siuint giuint ecuint etimerint rtclong1int powerint battint 3 KIUINTREG AND/OR 3 MKIUINTREG 3 AIUINTREG AND/OR 3 MAIUINTREG 6 PIUINTREG AND/OR 6 MPIUINTREG ledint rtclong2int lcdint ...
Page 173
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2 Register Set Physical address R/W 0x0A00 0080 R SYSINT1REG 0x0A00 008C R/W MSYNT1REG 0x0A00 0098 R/W NMIREG 0x0A00 009A R/W SOFTINTREG 0x0A00 0200 R SYSINT2REG 0x0A00 0206 R/W MSYSINT2REG 0x0B00 0082 R PIUINTREG ...
Page 174
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.1 SYSINT1REG (0x0A00 0080) Bit 15 14 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name KIUINTR AIUINTR R RTCRST 0 0 Other resets ...
Page 175
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) Bit Name 5 PIUINTR 4 Reserved 3 ETIMERINTR 2 RTCL1INTR 1 POWERINTR 0 BATINTR This register indicates level-1 interrupt requests’ status. Function PIU interrupt request 0 : Not occurred 1 : Occurred 0 is ...
Page 176
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.2 MSYSINT1REG (0x0A00 008C) Bit 15 14 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name MKIUINTR MAIUINTR R/W R/W R/W RTCRST 0 0 Other resets ...
Page 177
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) Bit Name 5 MPIUINTR 4 Reserved 3 METIMERINTR 2 MRTCL1INTR 1 MPOWERINTR 0 MBATINTR This register is used to enable/disable level-1 interrupts. Function Enables PIU interrupt 0 : Disable 1 : Enable 0 is ...
Page 178
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.3 NMIREG (0x0A00 0098) Bit 15 14 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name Reserved Reserved R RTCRST 0 0 Other resets ...
Page 179
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.4 SOFTINTREG (0x0A00 009A) Bit 15 14 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name Reserved Reserved R RTCRST 0 0 Other resets ...
Page 180
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.5 SYSINT2REG (0x0A00 0200) Bit 15 14 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name Reserved LCDINTR R RTCRST 0 0 Other resets ...
Page 181
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.6 MSYSINT2REG (0x0A00 0206) Bit 15 14 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name Reserved MLCDINTR R/W R R/W RTCRST 0 0 Other resets ...
Page 182
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.7 PIUINTREG (0x0B00 0082) Bit 15 14 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name Reserved PADCMD INTR R RTCRST 0 0 Other ...
Page 183
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.8 AIUINTREG (0x0B00 0084) Bit 15 14 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name Reserved Reserved R RTCRST 0 0 Other resets ...
Page 184
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.9 KIUINTREG (0x0B00 0086) Bit 15 14 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name Reserved Reserved R RTCRST 0 0 Other resets ...
Page 185
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.10 MPIUINTREG (0x0B00 008E) Bit 15 14 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name Reserved PADCMD INTR R/W R R/W RTCRST 0 0 Other ...
Page 186
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.11 MAIUINTREG (0x0B00 0090) Bit 15 14 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name Reserved Reserved R RTCRST 0 0 Other resets ...
Page 187
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.12 MKIUINTREG (0x0B00 0092) Bit 15 14 Name Reserved Reserved R RTCRST 0 0 Other resets 0 0 Bit 7 6 Name Reserved Reserved R RTCRST 0 0 Other resets ...
Page 188
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) This chapter describes the Power Management Unit (PMU) operation, register settings and power modes. 10.1 General The PMU performs power management within the V The PMU provides the following functions: • Reset control • ...
Page 189
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) Figure 10-1. Transition of V Standby mode (2) (1) Transition No. (1) STANDBY instruction (2) All interrupt requests (3) SUSPEND instruction <After transition> DRAM self refresh (4) Assertion of POWER Assertion and then deassertion ...
Page 190
... PLL, timer/interrupt function of the CPU core, interrupt clock (MasterOut), and RTC clock continue their operation. The contents of caches and registers in the CPU core are retained. The contents of connected DRAMs can be preserved by putting DRAMs into self-refresh mode. To enter to Suspend mode from Fullspeed mode, execute a Suspend mode sequence (see 10.6 Interface Control) first ...
Page 191
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) (4) Hibernate mode All clocks other than the RTC clock (32.768 kHz) are fixed to high level and the PLL operation stops. An RTC and a monitor for activation factors in the PMU continue ...
Page 192
... RSTSW# (Input) CAS# (Output) RAS(1:0)# (Output) (2) Preserving SDRAM data The SDRAM bit of the PMUINTREG register can be used to preserve the contents of SDRAM connected to the V 4181 during an RSTSW reset. When the SDRAM bit is set to 1, the PMU does not reset the memory controller. R Therefore, the memory controller completes current SDRAM access and performs CBR refresh cycle on an RSTSW reset ...
Page 193
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.4 Shutdown Control The operations of the RTC, peripheral units, and CPU core, and PMUINTREG register bit settings during a reset are listed below. For detail of the timing of each shutdown, refer to ...
Page 194
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.5 Power-on Control The causes of CPU core activation (mode change from shutdown mode or Hibernate mode to Fullspeed mode) are called activation factors. There are twenty activation factors: a power switch interrupt (POWER), ...
Page 195
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.5.1 Activation via Power Switch interrupt request When the POWER signal is asserted, the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated. After asserting the ...
Page 196
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.5.2 Activation via CompactFlash interrupt request When the CF_BUSY# signal is asserted, the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated. After asserting the POWERON ...
Page 197
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.5.3 Activation via GPIO activation interrupt request When any of the GPIO(15:0) signals are asserted, the PMU checks the GPIO(15:0) activation interrupt enable bits in the GIU. If GPIO(15:0) activation interrupts are enabled, the ...
Page 198
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.5.4 Activation via DCD interrupt request When the DCD1# signal is asserted, the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated. After asserting the POWERON ...
Page 199
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) Figure 10-9. Activation via DCD Interrupt Request (BATTINH = H) RTC (Internal) DCD1# (Input) POWERON (Output) MPOWER (Output) H BATTINH/BATTINT# (Input) Figure 10-10. Activation via DCD Interrupt Request (BATTINH = L) RTC (Internal) DCD1# ...
Page 200
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.5.5 Activation via ElapsedTime (RTC alarm) interrupt request When the alarm (alarm_intr signal) generated from the ElapsedTime timer is asserted, the PMU asserts the POWERON signal to provide an external notification that the CPU ...