T431616A-7S Taiwan Semiconductor Company, Ltd. (TSC), T431616A-7S Datasheet

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T431616A-7S

Manufacturer Part Number
T431616A-7S
Description
Manufacturer
Taiwan Semiconductor Company, Ltd. (TSC)
Datasheet
T431616A-7S
T431616A-7C
T431616A-7SI
T431616A-7CI
SDRAM
FEATURES
• 3.3V power supply
• Clock cycle time : 6 / 7 / 8 / 10 ns
• Dual banks operation
• LVTTL compatible with multiplexed address
• All inputs are sampled at the positive going
• Burst Read Single-bit Write operation
• DQM for masking
• Auto refresh and self refresh
• 32ms refresh period (2K cycle)
• MRS cycle with address key programs
• Available package type in 50 pin TSOP(II)
• Operating temperature :
PART NUMBER EXAMPLES
Taiwan Memory Technology, Inc. reserves the right P. 1
to change products or specifications without notice.
- CAS Latency ( 2 & 3 )
and 60-pin CSP.
edge of system clock
- Burst Length ( 1 , 2 , 4 , 8 & full page)
- Burst Type (Sequential & Interleave)
PART NO.
-
-
-5 ~ +70 °C
-40 ~ +85 °C
CH
TE
CYCLE TIME
CLOCK
7ns
7ns
7ns
7ns
FREQUENCY
143 MHz
143 MHz
143 MHz
143 MHz
MAX
PACKAGE
TSOP-II
TSOP-II
512K x 16bit x 2Banks Synchronous DRAM
GRNERAL DESCRIPTION
high data rate Dynamic RAM organized as
2 x 524,288 words by 16 bits , fabricated with high
performance CMOS technology . Synchronous
design allows precise cycle control with the use of
system clock I/O transactions are possible on every
clock cycle . Range of operating frequencies ,
programmable burst length and programmable
latencies allow the same device to be useful for a
variety of high bandwidth , high performance
memory system applications.
CSP
CSP
The T431616A is 16,777,216 bits synchronous
TEMPERATURE
OPERATING
-40 ~ +85 °C
-40 ~ +85 °C
-5 ~ +70 °C
-5 ~ +70 °C
1M x 16 SDRAM
Publication Date: DEC. 2000
T431616A
Revision: C

Related parts for T431616A-7S

T431616A-7S Summary of contents

Page 1

... CLOCK PART NO. CYCLE TIME T431616A-7S 7ns 7ns T431616A-7C 7ns T431616A-7SI 7ns T431616A-7CI Taiwan Memory Technology, Inc. reserves the right change products or specifications without notice. 512K x 16bit x 2Banks Synchronous DRAM GRNERAL DESCRIPTION The T431616A is 16,777,216 bits synchronous high data rate Dynamic RAM organized 524,288 words by 16 bits , fabricated with high performance CMOS technology ...

Page 2

... PIN PITCH) N.C DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 VDD VDDQ N.C N.C VSSQ DQ4 VSSQ VDDQ DQ0 N.C N.C VSSQ VDDQ VSSQ DQ15 VDDQ DQ11 N.C DQ8 DQ9 DQ10 DQ12 DQ13 DQ14 VSS T431616A Publication Date: DEC. 2000 Revision: C ...

Page 3

... Data Input Register 512K x 16 512K x 16 Colum n Decoder Latency & Burst Length Program m ing Register LW E LCAS Tim ing Register CS RAS CAS W E T431616A LW E LDQM DQ i LDQM LW CBR L(U)DQM Publication Date: DEC. 2000 Revision: C ...

Page 4

... Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. T431616A active. Publication Date: DEC. 2000 Revision: C ...

Page 5

... ≤ 10ns acceptable. ≤ 10ns acceptable. + 0.3V , all other pin are not under test = 0V. DD ≤ Symbol Min C 2.5 CLK C 2.5 ADD C 4.0 OUT C 2.5 IN T431616A Value Unit -1.0 to 4.6 V -1 °C °C -55 to +125 =0V) Max. Unit Notes 3 +0. 0 ...

Page 6

... Input signals are stable CAS Latency 3 170 160 140 mA CAS Latency 2 170 160 140 mA t ≥ 170 160 140 ≤ CKE 1 mA T431616A Test Condition ≥ (min) , (min), (max), =15ns IL CC ≤ (max),CLK ...

Page 7

... Taiwan Memory Technology, Inc. reserves the right change products or specifications without notice. °C /-40 to +85 °C ) Value 3 1 1.4 See Fig.2 Output VOH(DC)=2.4,IOH=-2mA VOL(DC)=0.4,IOL=2mA T431616A Unit Vtt=1.4v 50 ohm ZO=50 ohm 30pf (Fig.2)AC Output Load Circuit Publication Date: DEC. 2000 Revision: C ...

Page 8

... (min) RAS t 100K (max) RAS (min (min) CDL t (min) RDL t (min) BDL t (min) CCD CAS latency=3 CAS latency=2 T431616A Unit Note -8 - CLK 2 2 CLK ...

Page 9

... CC 8 8 SAC - 1.5 1. SLZ - 5 SHZ - T431616A -8 -10 Unit Note Min Max Min Max 2 ...

Page 10

... T431616A-6S t CAS RC Frequency Latency 60ns 166MHz(6.0ns 143MHz(7.0ns 125MHz(8.0ns 111MHz(9.0ns 100MHz(10.0ns T431616A-7S t CAS RC Frequency Latency 63ns 143MHz(7.0ns 125MHz(8.0ns 111MHz(9.0ns 100MHz(10.0ns 83MHz(12.0ns T431616A-8S ...

Page 11

... Use in future Vender Specific Mode Register Set Burst length Wrap type Latency mode T431616A v = Valid x = Don’t care Bit2-0 WT=0 WT=1 000 1 1 001 2 2 010 4 4 011 8 8 100 R R 101 R R 110 ...

Page 12

... Taiwan Memory Technology, Inc. reserves the right P.12 to change products or specifications without notice. Sequential Addressing Sequence (decimal) 0,1 1,0 Sequential Addressing Sequence (decimal) 0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2 Sequential Addressing Sequence (decimal) 0,1,2,3,4,5,6,7 1,2,3,4,5,6,7,0 2,3,4,5,6,7,0,1 3,4,5,6,7,0,1,2 4,5,6,7,0,1,2,3 5,6,7,0,1,2,3,4 6,7,0,1,2,3,4,5 7,0,1,2,3,4,5,6 T431616A Interleave Addressing Sequence (Decimal) 0,1 1,0 Interleave Addressing Sequence (Decimal) 0,1,2,3 1,0,3,2 2,3,0,1 3,2,1,0 Interleave Addressing Sequence (Decimal) 0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0 Publication Date: DEC. 2000 ...

Page 13

... (V=Valid , X=Don’t Care , H=Logic High , L=logic Low Program keys.(@MRS after the end of burst. RP T431616A / Row Address Column ...

Page 14

... SH *Note2. *Note2 *Note3 *Note3 SRC SLZ Write Read T431616A *Note4 *Note2 Bs Bs *Note4 Rb Qc Row Active Precharge Publication Date: DEC. 2000 Revision :Don't care ...

Page 15

... BA control bank precharge when precharge command is asserted / Taiwan Memory Technology, Inc. reserves the right P.15 to change products or specifications without notice. Bank A Bnak B Operation precharge Bank A Bank B Both Banks T431616A /AP in read/wirte command. 10 Publication Date: DEC. 2000 Revision: C ...

Page 16

... fre s h T431616A ...

Page 17

... +CAS latency-1)+ CC RCD T431616A ...

Page 18

... RDL T431616A ...

Page 19

... T431616A ...

Page 20

... rite ( rite ( T431616A ...

Page 21

... T431616A ...

Page 22

... before internal precharge start. RAS T431616A ...

Page 23

... T431616A ite ...

Page 24

... T431616A ...

Page 25

... rite ( RDL T431616A ...

Page 26

... ‘High’ at MRS (Mode Register Set). 9 T431616A ...

Page 27

... A c tiv tiv try prior to Row active command. SS T431616A ...

Page 28

... RAS T431616A ...

Page 29

... Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. Taiwan Memory Technology, Inc. reserves the right P.29 to change products or specifications without notice. Auto Refresh Cycle i fre s h T431616A ...

Page 30

... REF 11.96 0.455 0.463 10.29 0.394 0.400 0.60 0.016 0.020 0.031 REF 0.031 BSC - 0.005 - 0.25 0.005 - T431616A θ 2(4X GAGE θ 3 (4X) DEFAULT A θ "A" SECTION B-B b1 Max 0.047 0.006 0.041 0.018 0.016 0.008 0.006 0.830 ...

Page 31

... Dimension in inch Max Min Nom 6.50 0.248 2.52 10.20 0.394 0.398 - - 0.154(typ 0.358(typ 0.026(typ 0.026(typ) 0.40 0.014 - 0.40 0.014 - 0.32 0.009 0.11 1. 0.008 0.48 0.017 0.018 T431616A BOTTOM VIEW Max 2.56 0.40 0.016 0.016 0.13 0.039 - 0.019 Publication Date: DEC. 2000 Revision: C ...

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