GS74116J-15 GSI Technology, GS74116J-15 Datasheet

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GS74116J-15

Manufacturer Part Number
GS74116J-15
Description
15ns 256K x 16 4Mb asynchronous SRAM
Manufacturer
GSI Technology
Datasheet
1.GS74116J-15.pdf (14 pages)
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
Features
• Fast access time: 8, 10, 12, 15ns
• CMOS low power operation: 170/145/130/110 mA at min.cycle time.
• Single 3.3V ± 0.3V power supply
• All inputs and outputs are TTL compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: -40° to 85°C
• Package line up
Description
The GS74116 is a high speed CMOS static RAM organized as
262,144-words by 16-bits. Static design eliminates the need for exter-
nal clocks or timing strobes. Operating on a single 3.3V power supply
and all inputs and outputs are TTL compatible. The GS74116 is avail-
able in a 7.2x11.65 mm Fine Pitch BGA package, 400 mil SOJ and
400 mil TSOP Type-II packages.
Pin Descriptions
Rev: 2.02 3/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
J: 400mil, 44 pin SOJ package
TP: 400mil, 44 pin TSOP Type II package
U: 7.20mm x 11.65mm Fine Pitch Ball Grid Array package
DQ
Symbol
A
0
1
WE
V
V
CE
UB
OE
NC
to A
to DQ
LB
DD
SS
17
16
Lower byte enable input
Upper byte enable input
4Mb Asynchronous SRAM
Output enable input
+3.3V power supply
Write enable input
Chip enable input
Data input/output
(DQ9 to DQ16)
Address input
(DQ1 to DQ8)
Description
No connect
Ground
256K x 16
1/14
SOJ 256K x 16 Pin Configuration
Fine Pitch BGA 256K x 16 Bump Configuration
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
V
V
A
WE
A
A
A
A
CE
DD
A
A
A
A
A
SS
12
15
14
13
16
4
3
2
1
0
1
2
3
4
5
8
A
B
C
D
E
F
G
H
7.2x11.65mm 0.75mm Bump Pitch
DQ
DQ
DQ
V
V
DQ
NC
LB
1
DD
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
16
14
11
9
DQ
DQ
DQ
DQ
A
OE
NC
UB
2
12
15
13
12
10
Top view
Top View
44 pin
SOJ
A
A
A
NC
A
A
A
A
3
17
10
13
0
3
5
8
© 1999, Giga Semiconductor, Inc.
A
A
A
A
A
A
A
A
4
16
11
14
1
4
6
7
9
Center V
GS74116TP/J/U
DQ
DQ
DQ
DQ
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
WE
A
27
26
25
24
23
CE
A
8, 10, 12, 15ns
5
15
2
2
4
5
7
DQ
DQ
V
DQ
DQ
V
NC
NC
DD
6
SS
A
A
A
OE
UB
LB
DQ
DQ
DQ
DQ
V
V
DQ
DQ
DQ
DQ
NC
A
A
A
A
A
3.3V V
DD
1
3
6
8
5
6
7
SS
DD
8
9
10
11
17
16
15
14
13
12
11
10
9
& V
DD
SS
N

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GS74116J-15 Summary of contents

Page 1

SOJ, TSOP, FP-BGA Commercial Temp 4Mb Asynchronous SRAM Industrial Temp Features • Fast access time: 8, 10, 12, 15ns • CMOS low power operation: 170/145/130/110 mA at min.cycle time. • Single 3.3V ± 0.3V power supply • All inputs and ...

Page 2

TSOP-II 256K x 16 Pin Configuration Block Diagram _____ LB _____ Rev: 2.02 3/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com ...

Page 3

Truth Table Note: X: “H” or “L” Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Output Voltage Allowable power dissipation Storage ...

Page 4

Recommended Operating Conditions Parameter Supply Voltage for -10/12/15 Supply Voltage for -8 Input High Voltage Input Low Voltage Ambient Temperature, Commercial Range Ambient Temperature, Industrial Range Note: 1. Input overshoot voltage should be less than V 2. Input undershoot voltage ...

Page 5

Power Supply Currents Parameter Symbol Test Conditions CE V Operating All other inputs Supply Current Min. cycle time OUT CE Standby All other inputs I SB1 Current V IH Min. cycle ...

Page 6

AC Characteristics Read Cycle Parameter Read cycle time Address access time Chip enable access time (CE) Byte enable access time (UB, LB) Output enable to output valid (OE) Output hold from address change Chip enable to output in low Z ...

Page 7

Read Cycle Address CE UB Data Out Write Cycle Parameter Write cycle time Address valid to end of write Chip enable to end of write Byte enable to end of write Data set ...

Page 8

Write Cycle 1: WE control Address Data In Data Out Write Cycle 2: CE control Address Data In Data Out Rev: 2.02 3/2000 Specifications cited are subject to change without ...

Page 9

Write Cycle 3: UB, LB control Address Data In Data Out Rev: 2.02 3/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. tWC tAW tAS tCW tBW tWP tDW tDH ...

Page 10

Pin, 400 mil SOJ Rev: 2.02 3/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Symbol ...

Page 11

Pin, 400 mil TSOP- Rev: 2.02 3/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Symbol ...

Page 12

FP-BGA Pin A1 Index A A1 Pin Index Rev: 2.02 3/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 13

... GS74116J-12 400 mil SOJ GS74116J-15 400 mil SOJ GS74116J-8I 400 mil SOJ GS74116J-10I 400 mil SOJ GS74116J-12I 400 mil SOJ GS74116J-15I 400 mil SOJ GS74116U-8 Fine Pitch BGA GS74116U-10 Fine Pitch BGA GS74116U-12 Fine Pitch BGA GS74116U-15 Fine Pitch BGA GS74116U-8I ...

Page 14

Revision History Rev. Code: Old; Types of Changes New Format or Content Rev1.03c 3/1999; 1.04d 6/1999 1.04d 6/1999; 2.00 8/1999 GS741Rev2.01KRev 21 2/2000L GS74116 Rev2.01 2/2000L; Rev 2.02 3/2000N Rev: 2.02 3/2000 Specifications cited are subject to change without notice. ...

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