RTD2523 ETC, RTD2523 Datasheet
RTD2523
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RTD2523 Summary of contents
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... Realtek Flat Panel Display Controller RTD2523/2513 Confidential Revision 0.18 March 19, 2004 RTD2523/2513 ...
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... Realtek Revision History Rev. l 0.18 Pin-Description modification of TCON function in TTL output interface l Explanation for register DV_Total Description 2 RTD2523/2513 Date March 2004 ...
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... Dithering logic for 18-bit panel color depth enhancement Output Interface l Built-in display timing generator and fully programmable l (RTD2523) 1 and 2-pixel/clock panel support and up to 140MHz l (RTD2513) 1 and 2-pixel/clock panel support and up to 95MHz l Scaler internal LSB/MSB swap, odd/even swap and red/blue group swap. ...
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... Realtek 2. RTD2523/2513 Pin-Out Diagram DPLL_GND 3 DPLL_VDD 4 APLL_VDD 5 PLL_TST1 6 PLL_TST2 7 APLL_GND 8 TMDS_TST/PWM1 9 TMDS_GND 10 TMDS_VDD 11 REXT 12 TMDS_VDD 13 RX2P 14 RX2N 15 TMDS_GND 16 RX1P 17 RX1N 18 TMDS_VDD 19 RX0P 20 RX0N 21 TMDS_GND 22 RXCP 23 RXCN 24 TMDS_GND 25 TMDS_VDD 26 ADC_GND 27 ADC_REFIO 28 ADC_VDD ADC_GND 32 SOG ADC_VDD 36 R+ ...
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... Parallel port data [1] / TCON [4] / TTL BBLU [0] 52 Parallel port data [2] / TCON [3] / TTL BBLU [1] 51 Parallel port data [1] / TCON [4] / PWM2 50 Serial control I/F clock 111 Serial control I/F chip select 56 RESET output for Micron 5 RTD2523/2513 Note 1.20V (3.3V) (3.3V) (3.3V) (10), (4), (5) (2), (4), (5) Note (3.3V) (3.3V) 3.3V tolerance Note (2), (3), / 2mA ...
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... T10 TOBP BRED [4] / BRED [4] T11 TOAP BRED [3] / BRED [3] T12 TOAP BRED [2] / BRED [2] T13 TEDP ABLU [7] / ABLU [7] T14 TEDN ABLU [6] / ABLU [6] T15 6 RTD2523/2513 6 bits Single Note TTL S[3] / (1), (2), (3)/ TCON[2] / 2mA PWM2 S[2] / (1), (2), (3)/ TCON[3] 2mA S[1] / (1), (2), (3)/ TCON[4] 2mA PWM2 / (1), (2), (3)/ COUT / 2mA TCON[13] ...
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... V [1] BRED [1] V [2] BRED [0] V [3] AGRN [1] V [4] AGRN [0] V [5] DHS DHS V [6] DVS DVS V [7] DENA DENA VCLK DCLK DCLK 7 RTD2523/2513 ABLU [5] ABLU [4] ABLU [3] ABLU [2] TCON [1] TCON [0] AGRN [7] AGRN [6] AGRN [5] AGRN [4] AGRN [3] AGRN [2] ARED [7] ARED [6] ARED [5] ARED [4] ARED [3] ARED [2] PWM2 / (9) COUT / ...
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... DDC serial control I/F clock / TCON [0] / TTL BBLU [1] 47 DDC serial control I/F data input / output / TCON [1] / PWM1 / TTL BBLU [0] 126 DDC serial control I/F clock / TCON [5] 125 DDC serial control I/F data input / output / TCON [7] / PWM1 8 RTD2523/2513 Note (3.3V) (3.3V) (3.3V) (3.3V) Note (1), (2), (3), (5), (8), (2), (8), (9) (2), (8), (9) 6bit dual TTL cannot ...
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... Internal 75K Ohms pull low resistor. (5) Schmitt trigger CMOS Input (Vt=1.4-~2.2V); (6) Open-Drain, Output Drive low & Pull-high. (7) Bi-directional input/output (8) Programmable driving current (2~10mA) (9) TTL output 5V & 3.3V (10) 4V tolerance pad Pin No 49,121 VCCIO: 2 48,120 GNDIO: 2 58,71,83,95,110 PVCC: 5 57,72,84,96,109 PGND: 5 45,69,98,127 VCCK: 4 44,70,97,128 GNDK RTD2523/2513 Description ...
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... TCON RTD2523 Flat Panel Display Parallel Port Reset 24.576MHz IIC Color FIFO Conversion Control Scaling Up Register Color Processing MCU 10 RTD2523/2513 LCD Panel Row/Column 5C Driver 48D 5C TTL Signal LCD Panel 48D RSDS Signal 48D LCD Panel 5C 20 LVDS Signal LCD Panel Panel ...
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... Bits P0, P1, P2, P3, have states dependent on the states of the bits F, V and H as shown below. At the receiver this permits one-bit errors to be corrected and two-bits errors to be detected. xxx Cr718 Y719 EAV 80 10 … Bit 4(H) H=0 in SAV H=1 in EAV 11 RTD2523/2513 Y1 U2 Timing reference Blanking code period Bit 3(P3) Bit 2(P2) Bit 1(P1) Bit 0(P0) Protection bits ...
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... Inside RTD, there are four registers IPH_ACT_STA, IPH_ACT_WID, IPV_ACT_STA & IPV_ACT_LEN to define input capture window for the selected input video on either input port while programmed analog input mode. The horizontal sync (IHS) & vertical sync (IVS) signals are used from the selected port to determine the capture window region. RTD2523/2513 12 ...
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... Realtek IHS IVS IPV_ACT_STA IPV_ACT_LEN Horizontal blanking region (back porch) IPH_ACT_STA IPH_ACT_WID Figure 5 Input Capture Window Vertical blanking region (back porch) Input Capture Window Vertical blanking region (front porch) 13 RTD2523/2513 Horizontal blanking region (front porch) ...
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... Figure 6 Single Pixel Mode Display Data Timing DHCLK DEN DA/RGB DB/RGB Figure 7 Double Pixel Mode Display Data Timing xxx rgb0 rgb1 rgb2 xxx xxx rgb0 rgb2 rgb4 xxx rgb1 rgb3 rgb5 14 RTD2523/2513 rgb3 rgb4 rgb5 rgb6 rgb8 rgb10 rgb7 rgb9 rgb11 ...
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... Horizontal blanking region (back porch) DV_ACT_END DV_BKGD_END DV_TOTAL DH_HS_END DH_BKGD_STA DH_ACT_STA DH_ACT_END DH_BKGD_END DH_TOTAL Figure 8 Display Active Window Diagram Vertical blanking region (back porch) Background Region Display Active Window Vertical blanking region (front porch) 15 RTD2523/2513 DVS Horizontal blanking region (front porch) ...
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... The following diagram presents the data flow among the gamma correction, dithering, overlay MUX, OSD LUT and output format conversion blocks. Gamma 24 Correction Internal OSD 4 MUX Background Color 4 CR38 Figure 10 OSD color look-up table data path diagram + Gamma Correction Dithering 24 24 Conversion 16x24 color 4 24 look-up table 16 RTD2523/2513 To Dithering Output Format 24/48 ...
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... Of course, you can force this clock from external oscillators through pins REFCLK for your own applications. REFCLK1 Control Bit0 Figure 11 PLL System Control Diagram Spread-Spectrum function is also build in DCLK to reduce EMI while using TCON. You can control the SSP_I, SSP_W, and FMDIV to fine-tune the EMI. Control Bit1 CLK PLL 17 RTD2523/2513 Internal CLK ...
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... R Write INC : 0 - Address Auto-Inc Data1 Data0 R Read INC : 1 - Non-Address Auto-Inc RTD2523/2513 STOP Data2 STOP ...
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... A [1] A [5] INC D0 [1] D0 [5] D1 [1] D1 [5] D2 [1] D2 [5] SDIO [2] A [2] A [6] SDIO [3] A [3] A [7] Reset end SENSE SENSE Data 0 Data [2] D0 [6] D1 [2] D1 [6] D2 [ [3] D0 [7] D1 [3] D1 [7] D2 [3] D2 [7] Figure 16 Parallel Port Timing 19 RTD2523/2513 3.3V Parallel port 3.3V 0V Serial port Data ...
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... For the reset-out function, the characteristics are below: Parameter Symbol Detection Voltage -V det Release Voltage +V det Delay Time td +3.3V +V det -V det td +5V Figure 18 The RESET_OUT Timing Diagram Die RESET_OU T RESETB RESETB Package RESET_IN Min. Typ. 1.8 2.4 2 RTD2523/2513 Die RESET_OU T Package RESET_IN Max. Unit RESET_OUT ...
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... RTD supports TTL, LVDS and RSDS output interface. After power on, display port is high impedance. Firmware can set its control register in TCON address 0x03[7:6] to select output interface. Refer to Pin Out Diagram for output pin definition. RSDS interface Input HSYNC Output HSYNC 21 RTD2523/2513 ...
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... Swap” in 0x21[6] can swap red-channel data and blue-channel data. “Display MSB/LSB Data Swap” in 0x21[5] can swap bit order between “bit7 0” and “bit0 7”. “TTL Display B port Blue [1:0] Location” in TCON register 0x04[4] select where B port RTD2523/2513 22 ...
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... Spectrum FMDIV” in 0x99[3] control spreading frequency 33k or 66kHz. Fixed the Number of DCLK in a Frame “Enable the Fixed DVTOTAL & Last Line Length” in 0x5A[4] makes there are fixed DVTOTAL and Last Line Length in every frame. Fixed Last Line Length[10: 0x59 and RTD2523/2513 23 ...
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... Realtek 0x5A[2:0], and DVTOTAL[10: register 0x97 and 0x98[2:0]. Output frame is synchronized with input frame by selecting higher-frequency DCLK and lower-frequency DCLK – N*dF according to the position of Display VS leading edge controlled in register 0x99[1:0] and dF is DCLK*2^(-15). RTD2523/2513 24 ...
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... If an overflow in the input data capture buffer occurs, this bit is set to “1” Line Buffer Underflow status (Frame Sync Mode underflow in the line-buffer occurs, this bit is set to “1”. Write to clear status. RTD2523/2513 Function Function 25 Default: 81h Default: 00h ...
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... Realtek Address: 02 HOSTCTRL Bit Mode 7 R Display Support 0: XGA (RTD2513/2013) 1: SXGA (RTD2523/2023) 6:5 --- Reserved 4 R/W SOG_Mode 0: DC-offset, using POLY R 1: DC-offset, using MOS R 3 --- Reserved 2 R/W Power Down Mode Enable 0: Normal 1: Enable power down mode 1 R/W Power Saving Mode Enable (except sync processor & serial port): ...
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... Input HS Signal Polarity Inverted 0: Not inverted (HS = positive polarity) 1: Inverted (HS = negative polarity) 1 R/W Input ENA Signal Polarity Inverted 0: Not inverted (input high active) 1: Inverted (while input low active) 0 R/W Input Clock Polarity 0: Rising edge latched 1: Falling edge latched RTD2523/2513 Function Function 27 Default: 00h Default: 00h ...
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... This bit set to ‘1’ indicates that the read before display SRAM is not ready 6:2 --- Reserved. 1 R/W Internal IRQ Enable: 0: Disable these interrupt. 1: Enable these interrupt. The DDC & Status0 IRQ enable will be logically “ORed” together. 0 --- Reserved RTD2523/2513 Function Function Function Function Function Function Function Function Default: xxxx_xx00b Function 28 ...
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... Red Channel Test Pattern Digitized Result. The test pattern digitized result after HSYNC leading edge about PTNPOS pixel. Address: 12 PTNGD Bit Mode 7:0 R Green Channel Test Pattern Digitized Result. Address: 13 PTNBD Bit Mode 7:0 R Blue Channel Test Pattern Digitized Result. RTD2523/2513 Function Default: 00xx_xxxxb Function Function Function Function 29 ...
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... No invert 1: Invert 2 R/W ODD to Control FS_Delay_Fine_Tuning 0: Disable 1: Enable (FS_Delay_Fine_Tuning must set enable) 1 R/W Internal ODD-signal inverse for video-compensation 0: No invert 1: invert 0 R/W Internal ODD signal selection 0: ODD signal (from EAV) 1: Internal Field Detection ODD signal (Also support under DVI input) RTD2523/2513 Function 30 Default: 00h ...
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... C8000h = C8h, 00h, 0h. Address: 1A HV_SCA_L (Horizontal/Vertical Scale Factor Low) Bit Mode 7:6 R/W Bit [3:2] of horizontal scale factor 5:4 R/W Scale Up Horzontial Latch Delay Fine Tune 3:2 R/W Bit [3:2] of vertical scale factor 1:0 R/W Scale Up Vertical Latch Delay Fine Tune RTD2523/2513 Function Function Function Function Function Default: xx00xx00b Function 31 Default: 00h ...
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... IENA Start Event Status 1: If the IENA start event occurred since the last status read 0 R IVS Start Event Status 1: If the IVS start event occurred since the last status read Write to clear status. RTD2523/2513 Function Function Function Function Function 32 Default: C4h ...
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... Display Horizontal Sync output inverted logic 1 R/W Display Data Enable (DEN) Output Invert Enable: 0: Display Data Enable output normal active high logic 1: Display Data Enable output inverted logic 0 R/W TMDS_TEST 34 Data Output 0: Disable 1: Enable ( only when TTL mode, 24 bit output ) RTD2523/2513 Function Function 33 Default: 00h Default: 00h ...
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... The Width Bit [9:5] of Last Line Before Sync in Frame Sync Mode 1 2:0 R/W Display Horizontal Background end: High Byte [10:8] Determines the number of DCLK cycles from leading edge of DHS to the start of horizontal blanking. REG_2C[7:3] ®_26[7:3] indicates the width (counted by two pixel) of last line before VSYNC in frame sync mode 1. RTD2523/2513 Function Function Function Function Function ...
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... Auto fine tune delay function over min. margin status. 3 R/W DVS sync with x4 clock 0: Disable 1: Enable 2:0 R/W Display Vertical Active Region Start: High Byte [10:8] Write to clear status. Determines the number of lines from leading edge of DVS to first line of active region. RTD2523/2513 Function Function Function Function Default: 00000xxxb Function Function Default: 000000xxxb Function 35 ...
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... Display Vertical Background end: High Byte [10:8] Determines the number of lines from leading edge of DVS to the line of start of vertical blanking. Address: 38 IV_DV_LINES (IVS to DVS Lines) Bit Mode 7:0 R/W IVS to DVS Lines: (Only for FrameSync Mode) The number of input HS from input VS to output VS. RTD2523/2513 Function Function Function Function Function 36 ...
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... Select the internal PLL clock source as DPLL output (PWM0 output to REFCLK) 01: Select the external REFCLK clock source as DPLL output 10: Select the internal PLL clock source as DPLL & REFCLK output 11: Select the internal PLL clock source as DPLL output (Video odd/even from EAV output to REFCLK) RTD2523/2513 Function Function Function 37 ...
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... The line number of Display HS is equal to Display Vertical Total, this bit is set to “1”. Write to clear status Max. Measure Clear 0: clear after finish 1: write ‘1’ to clear PE Max. Value 5 R/W PE Max. Measure Enable 0: Disable 1: Enable PE Max. Measurement 4 Max Value RTD2523/2513 Function Function 38 Default: 00h Default: 00h ...
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... Color Processing Clock (CPCLK) Duty Fine-tune Enable: 0: Disable. 1: Enable CPCLK duty fine-tune (setting in 3E_bit3:0) 1 R/W Internal Display Clock (IDCLK) Duty Fine-tune Enable: 0: Disable. 1: Enable IDCLK duty fine-tuner (setting in 3E_bit7:4) 0 R/W Internal Display Clock (IDCLK) Invert. 0: Disable 1: IDCLK invert enable. RTD2523/2513 Function Function 39 Default:00h ...
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... Enable Vertical Line Compare Function 0: Disable 1: Enable 6 R/W Gating Vertical Line Compare Function to IRQ 5 R Vertical Line Compare Status (for Polling). Write to clear 4 R/W Select Compare Source: 0: Input Side 1: Display Side 3 -- Reserved RTD2523/2513 Function Function Function Function Function Function Function Function Function 40 Default: 00h ...
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... Realtek 2:0 R/W Select Vertical Line –Low Byte [2:0] Address: 49 EVENT_LOCATION Bit Mode 7:0 R/W Select Vertical Line --High Byte [11:3] RTD2523/2513 Function 41 Default: 00h ...
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... Sync-On-Green Enable: 0: Disable; 1: Enable (set “1” to Sync-Mode-Select at the same time) 0 R/W Sync Mode Select: 0: Separate H & Composite Sync from HSYNC or Green Address: 4C SYNC_POR (H & V SYNC Polarity Measured Result) Bit Mode RTD2523/2513 Default: Function Function Function 42 00h Default: 00h Default: 00h ...
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... R/W HSYNC & VSYNC Measured Mode 0: HS period counted by crystal clock & VS period counted resolution counted by input clock & V resolution counted by ENA (Get the correct resolution which is triggered by enable signal, ENA) RTD2523/2513 43 ...
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... MEAS_VS_HI (VSYNC High Period Measured Result) Bit Mode 7:0 R Input VSYNC Period Measurement Result: Low Byte[7:0] Address: 54 MEAS_VS_HI (VSYNC High Period Measured Result) Bit Mode 7 R 6-iclk-delay HS level latched by VS rising edge RTD2523/2513 Function Default: 8’bx000xxxx Function Function Function Function Default: Function Function Default: 8’bxxx00xxx Function 44 ...
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... Feedback HSYNC is synchronized by the positive edge of the input clock 1: Feedback HSYNC is synchronized by the negative edge of the input clock 3 R/W VSYNC Synchronize Edge 0: latch VS by the positive edge of input HSYNC 1: latch VS by the negative edge of input HSYNC 2:0 R Input VSYNC Period Measurement Result: High Byte[10:8] This result is expressed in terms of input HS pulses RTD2523/2513 45 ...
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... Interleaving Line Buffer Line Bufer: Low Byte [7:0] Address: 58 Display Data Bus Interleaving Line Buffer Length High Byte Bit Mode 2 R/W Display Data Bus Interleaving Enable 0: Disable 1: Enable 1:0 R/W Interleaving Line Buffer Line Bufer: High Byte [9:8] RTD2523/2513 Function Function Function Function 46 Default: 00h Default: 00h ...
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... Disable 1: Enable 6 R/W RSDS_TET_EN 0: Disable 1: Enable 5 R/W SSCG_TST_EN Test Enable 0: Disable 1: Enable(SDMOUT[3:0] will be pass to V8_DATA[3:0]) 4 R/W Enable the Fixed DVTOTAL & Last Line Length Function 0: Disable 1: Enable 3 R/W Enable DDS Spread Spectrum Output Function 0: Disable 1: Enable 2:0 R/W Fixed Last Line Length [10:8] RTD2523/2513 Function Default: 0000_0xxxb Function 47 ...
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... Enable Look-Up Table for Gamma Correction Coefficient: 0: disable the look-up table 1: enable the look-up table coefficient 1 R/W Enable Contrast Control Coefficient: 0: disable the coefficient 1: enable the coefficient 0 R/W Enable Brightness Control Coefficient: 0: disable the coefficient RTD2523/2513 Function Function 動作說明 Function 48 Default: 00h Default: 0x000000b Default: 00h ...
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... Old dithering(0x5A[7] = 0): When enable dithering table accessing, total size of coefficient table bits for RGB color. And the input data sequence is {c1, c0}, {c3, c2}, … {c15, c14 C10 C11 C12 C13 C14 C15 RTD2523/2513 Function Function Function Function Function Function Function Function Function Function 49 ...
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... New dithering(0x5A[7] = 1): One dithering sequence table contains 32element, s0, s1, … , s31. Each element has 2bit to index one of 4 dithering table. Input data sequence is {s3,s2,s1,s0}, {s7,s6,s5,s4}, … , {s31,s30,s29,s28 (2R+ choose sequence element, where R is Row Number / 2, and C is Column Number / 2. 4 dithering table, 0,1,2, RTD2523/2513 C8 C9 C10 C11 C12 C13 C14 C15 50 ...
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... OP_CRC_BYTE_0 (Output CRC Checksum Byte 0) Bit Mode 7:0 R Output CRC-24 bit 7~0 Address _CRC_BYTE_1 (Output CRC Checksum Byte 1) Bit Mode 7:0 R Output CRC-24 bit 15~8 Address _CRC_BYTE_2 (Output CRC Checksum Byte 2) Bit Mode 7:0 R Output CRC-24 bit 23~16 Function 1: Enable Function Function Function 51 RTD2523/2513 Default: FCh ...
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... Overlay 16x24 Look-Up-Table access port [7:0] Using this port to access overlay color plate which addressing by the above registers. The writing sequence into LUT is {R0, G0, B0, R1, G1, B1, … R15, G15, and B15} and the address counter will be automatic increment and circular from 0 to 47. RTD2523/2513 Function Function Function ...
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... V_SCALE_DH (Vertical scale down factor register) Bit Mode 7:0 R/W Vertical Scale Down Factor: High Byte [15:8] Registers { V_SCALE_DH, V_SCALE_DL} = (Yi / Ym) x (2^12) truncate. If not truncate, fill minus 1 Meanwhile vertical input width vertical memory write width RTD2523/2513 Function 10: 2ns delay 11: 3ns delay Function Function Function Function ...
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... Color Source Select for Detection: 00: B color 01: G color Address: 7E DIFF_THRESHOLD Bit Mode 7:0 R/W Difference Threshold Function Function Function 1: Enable Function Function Function Function 1: Odd 1: Enable Function Function 10: R color Function 54 RTD2523/2513 Default: 8’b0xxx_xxxx Default: 8’b0xxx_xxxx Default: 8’bxxxxxx00 Default: 8’bxxxxxx00 Default: 8’bxxxxxx00 ...
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... Diff/Pixel select 7E DifferenceThreshold 0:Pixel-value / 1:Diff Function 7F.6 7F.5 7F Function 55 RTD2523/2513 >= 0 DFF 1 DFF 7F.4 Accu/Comp select 0:Comp / 1:Accu Default: 00h 7F.3 7F.2 7F ...
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... ODD_CTRL (ODD Source Control Register) Bit Mode 7 R SAV/EAV two-bit error 6 R SAV/EAV one-bit error 5 R/W Auto switch when ADC-PLL non-lock 0: Disable 1: Enable 4 R/W Auto switch when overflow or underflow RTD2523/2513 Function Function Function Function Function Function Function Function Function Function Function Function Function Function 56 Default: 00h ...
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... Address: 8F FCLK (Scale Down Clcok) Fine Tune Bit Mode 7:3 -- Reserved 3 R/W Select VGIP clock 0: Reference clock 1: DDCSCL 2 R/W Select source of FCLK 0: original setting (default) 1: select ADC_CLK without combinational logic delay 1:0 R/W 0x8F[1] & 0x8F[0] FCLK fine tune 01: slowest 00: typical 1x: fastest RTD2523/2513 Function 57 Default: 00h ...
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... Data port for embedded OSD access Refer to the embedded OSD application note for the detailed. Address: 93 OSD_TEST Bit Mode 7:0 R/W Testing Pattern Address: 94 OSD_SCRAMBLE Bit Mode 7 R/W BIST Start 0: stop 1: start (auto clear) 6 R/W BIST Result 0: fail 1: success RTD2523/2513 Function Function Function Default: 00h Function Default: 00h Function 58 ...
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... Frequency Synthesis Select (F & F-N*dF) 00~11: N=1 dclk* 2^(-15) Address: 9A DCLK_FINE_TUNE_OFFSET_ LSB Bit Mode 7:0 R/W DCLK Offset [7:0] in Fixed DVTOTAL & Last Line Length Mode Address: 9B DCLK_FINE_TUNE_OFFSET_ MSB Bit Mode RTD2523/2513 Function Function Function Function Function Function Function 59 Default: 00h Default: 00h Default: 00h Default: 00h ...
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... RTD2523/2513 Default: 00h Default: 00h Phase [X ^^^^ 1000 0] 100 [0 1001 0] 104 [0 1010 0] [0 1011 0] 108 112 [0 1100 0] [1 1101 1] 116 ...
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... Reserved 5 R/W 1: Original power up sequence, turn on R/G when DE low 128 clocks 0: Turn On R/G channel when DE low 128 clocks and VS rising and falling appears 4 R Chbok: Detect Blue Channel DE low last 128 dclk High: Active, Low: Non-Active RTD2523/2513 Function Function 61 Default: 6Fh Default: EFh ...
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... Choose the freq stable time to turn on pllckon Perd Stable Time 00: 16us 32~48us 01: 64us 128~192us 10:256us 512~768us 11: 1ms 2~3ms 5:3 R/W HZTST: Enable TMDS TSTout pin. 0:Enable TSTOUTPAD 1:High impedance STSTPAD RTD2523/2513 Function Function Function Function 62 Default: 8Bh Default: 26h Default: 35h Default: 9f ...
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... High: When CRC done Low: When set 0xA6[7] 5 R/W Indicate VSYNC Polarity Mode: High: manual, decided by 0xA6[0] Low: auto, indicate by 0xA6[ Indicate VSYNC Polarity High: Negative Low: Positive 3 R/W Reserved R/W Reserved 1 R/W Always PRE-charge: RTD2523/2513 (power on latch to select parallel/serial port) Function 63 Default: 08h ...
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... Bit Mode 7 R/W tck_mode: High: TCK2 mode Low: Original 6:4 R/W f25sel: Decision latched data of F2x5FIFOT: check 12bit 000 [11:0] lat0 001 [23:12] lat1 010 [47:36] lat3 011 [59:48] lat4 10x [29:24] lat2 11x [35:30] lat2 Function Function Function Function Function 30bit 29:0 29:0 59:30 59:30 29:0 59:30 64 RTD2523/2513 Default: XX Default: XX Default: XX Default: 00h Default: 00h ...
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... If Red/Green/Blue FIFO overflow or underflow, These will set ‘1’, clear ‘0’ after read. 3 R/W Reserved 2 R/W OCLK divide 2: High: Enable Low: Disable 1:0 R/W Reserved F25CK Delay 2ns 01 : 2.7ns 10 : 3.7ns 11 : 4.7ns delay clock 1x from analog Address B0: TMDS CTL0~3 Signal Status RTD2523/2513 Function Function Function Function 65 Default: 90h Default: 00h Default: 00h Default: 00h Default:30h ...
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... DVI DDC Channel (Refers to the VESA “Display Data Channel Standard” for detailed, Address: BC DDC_ENABLE (DDC Channel Enable Register) Bit Mode 7:5 R/W DDC Channel Address Least Significant 3 Bits RTD2523/2513 Function Function Function Function Function Default: 00h Function Function DVI channel only support ...
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... The DDC channel index register will be auto increased one by one after each read or write cycle. Address: BE DDC_ACCESS_PORT (DDC Channel ACCESS Port) Bit Mode 7:0 R/W DDC SRAM Read/Write Port ** The DDC function can still work when Power_Down & Power_Save. ** After reset, the register will be set to default value, but the SRAM will keep original data. RTD2523/2513 Function Function 67 ...
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... Bit 2 ER5 ER4 ER3 ER2 EB0 EG5 EG4 EG3 VS*5 HS*5 EB5 EB4 EB7 EB6 EG7 EG6 OR5 OR4 OR3 OR2 68 RTD2523/2513 Default: 00h Default: 04h Default: 52h Bit 1 Bit 0 Bit 6 Bit 5 ER1 ER0 EG0 ER5 EG2 EG1 EB1 EB0 EB3 EB2 DEN*6 VS*5 ...
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... EB0 EG1 EG0 OR7 OR6 OR5 OR4 OB2 OG7 OG6 OG5 VS*1 HS*0 OB7 OB6 OB1 OB0 OG1 OG0 Function Function 69 RTD2523/2513 OG2 OG1 OB1 OB0 OB3 OB2 DEN*2 VS*1 OR7 OR6 RSV*3 OB7 Bit 1 Bit 0 Bit 6 Bit 5 ER3 ER2 EG2 ER7 EG4 EG3 ...
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... Bias Generator Adjust (0110) 3 R/W Bandgap of LVDS/RSDS Power on 0: Off 1: On 2:0 STSTL [2:0]: select test attribute R/W 000: High Impedance 001: VOCME 010: VBG 011: 60uA (20K ohm to GND) 1xx: TSTPLL (50 ohm to VDD) Power save & power down: set C0[7: C5[ RTD2523/2513 Function 70 Default: 60h ...
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... I_Code [11] / Overwrite return a new PFD calibrated value. 2 I_Code [10] / R/W 0: Old PFD 1: New PFD 1:0 I_Code [9:8] / For old I or New_I mechanism depending on 0xc9[0] & 0xc9[4] R/W Address: CB P_CODE Bit Mode 7 --- Reserved RTD2523/2513 Function Function Function Function 71 Default: 00h Default: 61h Default: 18h Default: 18h ...
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... Control-Register CC & CD will filled in when Control-Register CD is written. Address: CE PFD Calibrated Results Bit Mode 5:0 R/W PFD Calibrated Results This register determines the number of output pixel per horizontal line. PLL derives the sampling clock and data output Address: CF Reserved RTD2523/2513 -7 , P_Code=2 Function Function Function Default: 05h Default: 3Fh ...
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... Mode 7:6 R/W Watch Dog State Setting 00: WD active 01: WD take over 1x: WD sleep 5:4 R/W Watch Dog Voltage Setting Function Register) Function Function DPN=0x0A+2=12; Divider=1/4, = 24.576 x 127 / 65.024MHz. Function Function 73 RTD2523/2513 Default: 00010xx0b Default: 01111101b Default: 00001010b F_IN = 24.576MHz. Default: xx10_1111b Default: 0000011xb ...
Page 74
... PLL1's clock detector (0 is normal) cko PLL's ADC output clock fav3v fav signal (from DDS) PLL2's VCO output clock PLL1's VCO output clock BVS Video8 VS from EAV IRQ Low active Crystal signal input (3B[6]=1) 74 RTD2523/2513 Default: 0001xx10b Default: (0Bh) Default: 03h Default: 6Fh (Reference to 0xDD[7:6]) ...
Page 75
... PLL2's clock detector (0 is normal) (From DDS) (From DDS) PLL’ s GND BHS Video8 HS from SAV/EAV PLL’ s GND Table 2 Test-Pin Pair Setting Function Function Function Function (Reference to 0xEA[2]) Function Function Function 75 RTD2523/2513 Default: 10h Default: 0Ah Default: 04h Default: EFh Default: 1000_0xx0b ...
Page 76
... ADC Power Down 1: Normal Address: E7 ADC_REG_CUR_L Bit Mode 7:6 R/W ADC master bias current option: vicm, vocm buffer op bias 00 45u 01 60u 10 75u 11 90u 5:4 R/W ADC master bias voltage option: vicm voltage 00 0.98V 01 1.08V 10 1.20V 11 1.32V RTD2523/2513 Function Function Function Function Function Function 76 Default: 80h Default: 69h ...
Page 77
... ADC select divider ratio in test mode, hidden. 00 divided divided divided divided by 4 Address: EA ADC_REG_CLK Bit Mode 7 R/W ADC red channel select: 0: even 1: odd 6 R/W ADC green channel select: RTD2523/2513 Function are each 150ps. Function Function 77 Default: 15h Default: 10h Default: 05h ...
Page 78
... ADC Blue Channel Clamp Selection 0: To ground 1: To mid-scale Note: 0xEC[7] must be 0. Address Schmitt Trigger Control Bit Mode 7 R/W HS Power Down (only for Schmitt trigger new mode 0xED[5] =1) 0: Power down 1: Normal RTD2523/2513 Function Function Function 78 Default: 00h Default: 08h Default: 00h ...
Page 79
... After we get the threshold voltage by the table, we still can fine tune it: + Final Positive Threshold Voltage = V - 0.1* 0xED[ Final Negative Threshold Voltage = 1. 1.5V 1.0V 0xED [ 0xED [3:2] 0xED [1: 00 2. 2. 2. 2.6V 11 0.1* 0xED[4] 79 RTD2523/2513 + = 0.6V t ...
Page 80
... Enable the DDC_DATA_IN latched as an interrupt source 1 R/W 0: Disable the DDC_SUB latched as an interrupt source 1: Enable the DDC_SUB latched as an interrupt source 0 R/W 0: Disable the DDC_SLAVE latched as an interrupt source 1: Enable the DDC_SLAVE latched as an interrupt source RTD2523/2513 Function Function Function Function Function Default: 00h Function 80 ...
Page 81
... After reset, the register will be set to default value, but the SRAM will keep original data. Address: FF TMDS Hsync & Vsync Error Correction Bit Mode 2 R/W ADC Digital Filter 0: Disable 1: Enable 1:0 R/W TMDS Enhancement 00: orignal output 01: one pixel debouncing 10: one + eight pixels debouncing 11: one+ eight pixels debouncing & masking RTD2523/2513 Function Function Function Function 81 Default: 00h Default: 00h ...
Page 82
... Lowest Drive (2mA) ~ 111: Highest Drive (16mA) for TTL 000~111: (C2)*2 + (C1)*1 + (C1)*0.5 + 2.5 mA for RSDS 3 R/W OCLK Slew-Rate Control (pin112) 0: fast 1: slow 2:0 R/W OCLK Drive Current Control (pin112) 000: Lowest Drive (2mA) ~ 111: Highest Drive (16mA) for TTL Address: 02 PURE_TTL_PIN_DRV RTD2523/2513 Function Function Default: 0000_011xb Function Function Default: 00h 82 Default: 00h Default: 00h ...
Page 83
... ADC_DDC Enable 0: Disable 1: Enable 5 --- Reserved 4 R/W TTL Display B port Blue [1:0] Location (only for TTL 8bit mode) 0: From pin 52, 53 (must be serial port) 1: From pin 46, 47 (TCON 0x04[ R/W VIDEO-8 port Input / Output Enable 0: Output 1: Input RTD2523/2513 Function Function Function 83 Default: 40h Default: F8h ...
Page 84
... Notes triggered on rising edge of the DCLK Address: 0D TCON [0]_HE_LSB (TCON [0] Horizontal End LSB Register) Bit Mode 7:0 W Pixel count [7:0] at which TCON goes inactive Notes: If the register number is large than display format, the horizontal component is always on. RTD2523/2513 Function Function Function Function Function Function Function 84 ...
Page 85
... Select DCLK/4 when TCON [2] is “0” 101: Select DCLK/4 when TCON [2] is “1” 110: Select DCLK/8 when TCON [2] is “0” 111: Select DCLK/8 when TCON [2] is “1” -------------------------------------------------------------------------------------------------------------------- TCON [1] xx0: Normal TCON output xx1: Reverse-Control Signal output RTD2523/2513 Default: 00h Function 85 ...
Page 86
... EVEN data Output Inversion Controlled by TCON [0] is “1” ODD data Output Inversion Controlled by TCON [1] is “1” Address: 5F/67/6F/77 TC_DOT_MASKING_CTRL Bit Mode 7:3 R/W Reserved 2 R/W Red Dot Masking Enable 0: Disable 1: Enable 1 R/W Green Dot Masking Enable 0: Disable 1: Enable 0 R/W Blue Dot Masking Enable 0: Disable 1: Enable RTD2523/2513 Default: 00h Function 86 ...
Page 87
... TCON [5]_CTRL_REG Reserved TCON [6]_VS_REG (11) TCON [6]_HS_REG (11) TCON [6]_CTRL_REG Reserved TCON [7]_VS_REG (11) TCON [7]_HS_REG (11) TCON [7]_CTRL_REG Reserved TCON [8]_VS_REG (11) TCON [8]_HS_REG (11) TCON [8]_CTRL_REG Reserved TCON [9]_VS_REG (11) TCON [9]_HS_REG (11) TCON [9]_CTRL_REG Reserved TCON [10]_VS_REG (11) 87 RTD2523/2513 Default ...
Page 88
... Realtek 5D,5C, 62,61,60 65,64, 6A,69,68 6D,6C, 72,71,70 75,74, TCON [10]_HS_REG (11) TCON [10]_CTRL_REG TCON [10]_CTRL_REG TCON [11]_VS_REG (11) TCON [11]_HS_REG (11) TCON [11]_CTRL_REG TCON [11]_CTRL_REG TCON [12]_VS_REG (11) TCON [12]_HS_REG (11) TCON [12]_CTRL_REG TCON [12]_CTRL_REG TCON [13]_VS_REG (11) TCON [13]_HS_REG (11) TCON [13]_CTRL_REG TCON [13]_CTRL_REG 88 RTD2523/2513 ...
Page 89
... Byte0àByte1àByte2àByte0àByte1àByte2… (Address will auto increase) BIT A15 A14 A13 A12 A11 A10 BIT 000~EFF 89 RTD2523/2513 3.75k*3byte ...
Page 90
... For 3D window the right-bottom/top border color Byte 2 Bit Mode Gradient Polarity 0: Decrease 1: Increase Gradient Polarity 0: Decrease 1: Increase Gradient Polarity 0: Decrease 1: Increase 4:3 W Gradient level 00: 1 step per level 01: Repeat 2 step per level 10: Repeat 3 step per level 11: Repeat 4 step per level RTD2523/2513 Function Function Function 90 ...
Page 91
... Realtek 2 W Enable Red Color Gradient 1 W Enable Green Color Gradient 0 W Enable Blue Color Gradient RTD2523/2513 91 ...
Page 92
... Window 0 control Address: 103h Byte 0 Bit Mode 7:0 -- Reserved Byte 1 Bit Mode 7 -- Reserved 6:4 W 111: 7 level per gradient 110: 6 level per gradient 101: 5 level per gradient 100: 4 level per gradient 011: 3 level per gradient RTD2523/2513 Function Function Function Function Function Function Function Function 92 ...
Page 93
... It must be the same as bit[5:3] for 3D button thickness Byte 1 Bit Mode 7:4 W Window 1 shadow color index in 16-color LUT For 3D window the left-top/bottom border color 3:0 W Window 1 border color index in 16-color LUT For 3D window the right-bottom/top border color RTD2523/2513 Function Function Function 93 default: 00h ...
Page 94
... Window 1 end position Address: 106h Byte 0 Bit Mode 7:2 W Window 1 horizontal end [5:0] 2:0 -- Reserved Byte 1 Bit Mode 7:5 W Window 1 vertical end [2:0] line 4:0 W Window 1 horizontal end [10:6] pixel Byte 2 Bit Mode 7:0 W Window 1 vertical end [10:3] line End position must be increments of four. RTD2523/2513 Function Function Function Function Function Function Function 94 ...
Page 95
... Window 2 shadow/border height in line unit 000~111 line It must be the same as bit[5:3] for 3D button thickness Byte 1 Bit Mode 7:4 W Window 2 shadow color index in 16-color LUT For 3D window the left-top/bottom border color 3:0 W Window 2 border color index in 16-color LUT RTD2523/2513 Function Function Function Function Function 95 ...
Page 96
... Window 2 vertical end [2:0] line 4:0 W Window 2 horizontal end [10:6] pixel Byte 2 Bit Mode 7:0 W Window 2 vertical end [10:3] line End position must be increments of four. Window 2 control Address: 10Bh Byte 0 Bit Mode 7:0 -- Reserved Byte 1 Bit Mode RTD2523/2513 Function Function Function Function Function Function Function Function Function 96 ...
Page 97
... Window 3 shadow color index in 16-color LUT For 3D window the left-top/bottom border color 3:0 W Window 3 border color index in 16-color LUT For 3D window the right-bottom/top border color Byte 2 Bit Mode 7:0 W Reserved Window 3 start position Address: 10Dh Byte 0 Bit Mode RTD2523/2513 Function Function Function Function Function 97 default: 00h ...
Page 98
... Byte 0 Bit Mode 7:0 -- Reserved Byte 1 Bit Mode 7:4 -- Reserved 3:0 W Window 3 color index in 16-color LUT Byte 2 Bit Mode 7:5 W Reserved 4 W Shadow/Border/3D button 0: Disable 1: Enable 3:1 W Window 3 Type 000: Shadow Type 1 001: Shadow Type 2 RTD2523/2513 Function Function Function Function Function Function Function Function 98 default: 00h ...
Page 99
... Window 4 border color index in 16-color LUT For 3D window the right-bottom/top border color Byte 2 Bit Mode 7:0 W Reserved Window 4 start position Address: 111h Byte 0 Bit Mode 7:2 W Window 4 horizontal start [5:0] 2:0 -- Reserved Byte 1 Bit Mode 7:5 W Window 4 vertical start [2:0] line 4:0 W Window 4 horizontal start [10:6] pixel RTD2523/2513 Function Function Function Function Function 99 ...
Page 100
... Shadow/Border/3D button 0: Disable 1: Enable 3:1 W Window 4 Type 000: Shadow Type 1 001: Shadow Type 2 010: Shadow Type3 011: Shadow Type 4 100: 3D Button Type 1 101: 3D Button Type 2 110: Reserved 111: Border 0 W Window 4 Enable RTD2523/2513 Function Function Function Function Function Function Function 100 default: 00h ...
Page 101
... Repeat 2 step per level 10: Repeat 3 step per level 11: Repeat 4 step per level 2 W Enable Red Color Gradient 1 W Enable Green Color Gradient 0 W Enable Blue Color Gradient Window 5 start position Address: 115h Byte 0 Bit Mode RTD2523/2513 Function Function Function Function 101 ...
Page 102
... W Window 5 color index in 16-color LUT RTD2523/2513 Function Function Function Function Function Function Function 102 ...
Page 103
... Window 6 shadow color index in 16-color LUT For 3D window the left-top/ bottom border color 3:0 W Window 6 border color index in 16-color LUT For 3D window the right-bottom/top border color Byte 2 Bit Mode Gradient Polarity 0: Decrease 1: Increase RTD2523/2513 Function Function Function Function 103 default: 00h ...
Page 104
... Window 6 vertical start [10:3] line Window 6 end position Address: 11Ah Byte 0 Bit Mode 7:2 W Window 6 horizontal end [5:0] 1:0 -- Reserved Byte 1 Bit Mode 7:5 W Window 6 vertical end [2:0] line 4:0 W Window 6 horizontal end [10:6] pixel Byte 2 Bit Mode 7:0 W Window 6 vertical end [10:3] line RTD2523/2513 Function Function Function Function Function Function 104 ...
Page 105
... W Shadow/Border/3D button 0: Disable 1: Enable 3:1 W Window 6 Type 000: Shadow Type 1 001: Shadow Type 2 010: Shadow Type3 011: Shadow Type 4 100: 3D Button Type 1 101: 3D Button Type 2 110: Reserved 111: Border 0 W Window 6 Enable 0: Disable 1: Enable RTD2523/2513 Function Function Function 105 default: 00h ...
Page 106
... Repeat 3 step per level 11: Repeat 4 step per level 2 W Enable Red Color Gradient 1 W Enable Green Color Gradient 0 W Enable Blue Color Gradient Window 7 start position Address: 11Dh Byte 0 Bit Mode 7:2 W Window 7 horizontal start [5:0] 1:0 -- Reserved RTD2523/2513 Function Function Function Function 106 ...
Page 107
... W Window 7 color index in 16-color LUT Byte 2 00h Bit Mode 7 W Reserved 6 W Gradient function RTD2523/2513 Function Function Function Function Function Function Function Function 107 default: ...
Page 108
... W Gradient direction 0: Horizontal 1: Vertical 4 W Shadow/Border/3D button 0: Disable 1: Enable 3:1 W Window 7 Type 000: Shadow Type 1 001: Shadow Type 2 010: Shadow Type3 011: Shadow Type 4 100: 3D Button Type 1 101: 3D Button Type 2 110: Reserved 111: Border 0 W Window 7 Enable 0: Disable 1: Enable RTD2523/2513 108 ...
Page 109
... Realtek 3D Button Type 1 3D Button Type 2 109 RTD2523/2513 ...
Page 110
... Realtek width height Type 1 Type 2 start OSD appear range Window mask fade/in out function Type 3 Shadow in all direction transparent end 110 RTD2523/2513 Type 4 ...
Page 111
... W Rotation 0: Normal (data latch 24 bit per 24 bit) 1: Rotation (data latch 18 bit per 24 bit OSD enable 0: OSD circuit is inactivated 1: OSD circuit is activated When OSD is disabled, Double Width (address 0x002 Byte1[1]) must be disabled to save power. RTD2523/2513 Function Function Function 111 ...
Page 112
... Only window and character background blending 1 W Double width enable (For all OSD including windows and characters) 0: Normal 1: Double 0 W Double Height enable (For all OSD including windows and characters) 0: Normal 1: Double RTD2523/2513 Function Function Function default: xxxx_xxx0b Function 0:DCLK , 1:Crystal Clock Function 112 ...
Page 113
... Font downloaded swap control 0x: No swap 10: CCW 11: CW 5:0 -- Reserved Bit 7 6 Firmware CCW E A 23~12 bit(High) 11~0 bit(Low) Figure 3 Non-rotated memory alignments 23 Figure 4 Rotated memory alignments Base address offset Function 113 RTD2523/2513 ...
Page 114
... Realtek Address: 003h Byte 0 Bit Mode 7:0 W Font Select Base Address[7:0] Byte 1 Bit Mode 7:4 W Font Select Base Address[11:8] 3:0 W Font Base Address[3:0] Byte 2 Bit Mode 7:0 W Font Base Address[11:4] RTD2523/2513 Function Function Function 114 ...
Page 115
... One 2-bit font requires 18 * 24bit SRAM One 4-bit font requires 36 * 24bit SRAM Rn End C11 C12 C13 … … … 1-bit font start … … … … … … 11.25k bytes SRAM R2 R3 R… . Font Select Base Address + Row 0 font base 115 RTD2523/2513 … … Rn End ...
Page 116
... Each row must start with row-command, last word of OSD map must be end-command 6:5 W Reserved 4:2 W Character border/shadow 000: None 001: Border 100: Shadow (left-top) 101: Shadow (left-bottom) 110: Shadow (right-top) 111: Shadow (right-bottom Double character width Double character height RTD2523/2513 hardware Clock-Wise Function 116 (the ...
Page 117
... Row space color Byte 2 Bit Mode 7:0 W Row length Blank Command Byte 0 Bit Mode Blinking effect 0: Disable 1: Enable 5:0 W Reserved Function column space color 1/2/4LUT bg color the same as Character background ,4 true color mode, bg color is transparent Function unit: font base Function 117 RTD2523/2513 ...
Page 118
... When using border/shadow/ effect, the width of the 1-bit font should at least 6 pixel. Byte 1 Bit Mode 7:0 W Character Select [7:0] Byte 2 Bit Mode 7:4 W Foreground color Select one of 16-color from color LUT 3:0 W Background color RTD2523/2513 Function Function Function Function Function 118 ...
Page 119
... Add Byte0[4] as MSB for 16-color LUT. While 0 is special for transparent 5:3 W Foreground color 10 Select one of 8 color from color LUT Add Byte0[4] as MSB for 16-color LUT. 2:0 W Foreground color 01 Select one of 8 color from color LUT Add Byte0[4] as MSB for 16-color LUT. RTD2523/2513 Function Function Function 119 ...
Page 120
... Byte 2 Bit Mode 7:4 W (for Byte1[ Green color level MSB 4 bits for 8 bits color level (LSB 4 bits are 1111) 3:0 W (for Byte1[ Blue color level MSB 4 bits for 8 bits color level (LSB 4 bits are 1111) RTD2523/2513 Function Function Function 120 ...
Page 121
... The required number of character map is larger than RAM size. We must turn on double width or double height function to reduce the half of character map. So the basic unit to chessboard is 2x2 pixel. You can use larger chessboard instead of 2x2 pixels unit, such as 4x4 and so on. Gray level window 5 window 4 A window 3 window 2 window 1 window 0 Display Priority 121 RTD2523/2513 ...
Page 122
... Realtek We can display 256 gray level by gradient window, 8 and 16 gray level by character map. 32 and 64 gray level is not supported. RTD2523/2513 122 ...
Page 123
... VDD I 244 DVCC I 5.2 AVCC I 6 PVCC I 7.2 VDD I 5.6 DVCC I 0.6 AVCC I 1 PVCC V 2.4 VDD OH V GND 100 300 150 PD I -10 + -20 +20 LO 123 RTD2523/2513 UNITS ºC ºC ºC/W UNITS Ω Ω μA μA ...
Page 124
... Input control signals setup time for ICLK 2 TIPCH Input control signals hold time for ICLK 1 TIPDS Input data setup time for ICLK TIPDH Input data hold time for ICLK TIPDS TIPCS Figure 17 Input Signal Timing Min 2 1 124 RTD2523/2513 TIPDH TIPCH Max Unit ...
Page 125
... Output control signals setup time for TOPCH DCLK Output control signals hold time for TOPDS DCLK Output data setup time for DCLK TOPDH Output data hold time for DCLK TOPDS TOPCS Figure 18 Output Signal Timing Min 125 RTD2523/2513 TOPDH TOPCH Max Unit ...
Page 126
... Serial port input signal setup time for TSPIH SCLK Serial port input signal hold time for TSPOS Serial port output signal setup time for SCLK TSPOH Serial port output signal for SCLK SCLK TSPIS TSPIH TSPOS Min 2 8 1/3 1/2 126 RTD2523/2513 TSPOH Max Unit ns ns TCK TCK ...
Page 127
... Output fall time (20pf Load) Tof Duty cycle (20pf Load, at 1.5V) Tduty Clock Skew (20pf Load, at 1.5V) Tskw1 Jitter, Absolute (20pf Load) Tj1 Tcycle Tor Tof Mix Type Max From 0.8V to 2.0V,Vdd=3.3V From 2.0V to 0.8V,Vdd=3.3V DCLK 45 DCLK to DCLK DCLK 127 RTD2523/2513 Unit 2 250 ps 300 ps ...
Page 128
... Realtek Mechanical Specification 1.45 128 Pin Package RTD2523/2513 128 ...
Page 129
... Millimeter 4.General appearance spec. should be based on final visual inspection spec. TITLE : 128LD QFP ( 14x20 mm*2 ) PACKAGE OUTLINE -CU L/F, FOOTPRINT 3.2 mm LEADFRAME MATERIAL: APPROVE CHECK 0.10 REALTEK SEMI-CONDUCTOR CO., LTD 12 ° 129 RTD2523/2513 DOC. NO. 530-ASS-P004 VERSION 1 PAGE OF DWG NO. Q128 - 1 DATE MAR. 25.1997 ...