AX88196L ETC ETC, AX88196L Datasheet

AX88196L

Manufacturer Part Number

AX88196L

Description

AX88196L10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM

Manufacturer

ETC ETC

Datasheet

1.AX88196L.pdf (42 pages)

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Company:

Meier Automation Equipment Co., Limited

Part Number:

AX88196L

Manufacturer:

ASIX

Quantity:

20 000

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Features

ASIX ELECTRONICS CORPORATION

2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.

TEL: 886-3-579-9500

This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability

is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.

Product description

The AX88196 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet

Controller with embedded 8K*16 bit SRAM. The AX88196 supports both 8 bit and 16 bit local CPU interfaces

include MCS-51 series, 80186 series, MC68K series CPU and ISA bus. The AX88196 implements both 10Mbps and

100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard and supports both 10Mbps/100Mbps

media-independent interface (MII) and legacy pure 10Mbps SNI interface to simplify the design. Using Serial

Network Interface (SNI) transceiver, Home LAN PHY or 10BASE-2 BNC type media can be supported.

As well as, the chip also provides Standard Print Port (parallel port interface), can be used for printer server device or

treat as simple general I/O port.

System Block Diagram

IEEE 802.3u 100BASE-T, TX, and T4 Compatible

Single chip local CPU bus 10/100Mbps Fast

Ethernet MAC Controller

Embedded 8K * 16 bit SRAM

NE2000 register level compatible instruction

Support both 8 bit and 16 bit local CPU interfaces

include MCS-51 series, 80186 series and MC68K

series CPU

Support both 10Mbps and 100Mbps data rate

Support both full-duplex or half-duplex operation

Provides a MII port for both 10/100Mbps operation

Provides SNI I/F for Home LAN PHY or 10M

transceiver option

10/100BASE Local CPU Bus Fast Ethernet MAC Controller

with Embedded SRAM, SNI interface and Parallel Port

Always contact ASIX for possible updates before starting a design.

Addr H

Ctl BUS

AD BUS

Addr L

10/100BASE Fast Ethernet MAC Controller

FAX: 886-3-579-9558

AX88196

*IEEE is a registered trademark of the Institute of

*All other trademarks and registered trademark are the

Electrical and Electronic Engineers, Inc.

property of their respective holders.

Support EEPROM interface to store MAC address

External and internal loop-back capability

Support Standard Print Port, can also used as

general I/O port

128-pin LQFP low profile package

20MHz to 25MHz Operation, Dual 5V and 3.3V

CMOS process with 5V I/O tolerance. Or pure 3.3V

operation

Document No.: AX196-12 / V1.2 / May. 12 ’00

Home LAN

PHY/TxRx

10/100M

First Released Date : Dec/13/1999

Or 10M

PHY

Or General I/O Ports

Print Port

http://www.asix.com.tw

AX88196 L

RJ11

BNC

RJ45

Related parts for AX88196L

AX88196L Summary of contents

Page 1

Local CPU Bus Fast Ethernet MAC Controller with Embedded SRAM, SNI interface and Parallel Port Features IEEE 802.3u 100BASE-T, TX, and T4 Compatible Single chip local CPU bus 10/100Mbps Fast Ethernet MAC Controller Embedded bit SRAM ...

Page 2

AX88196 1.0 INTRODUCTION ...............................................................................................................................................4 1 .....................................................................................................................................4 ENERAL ESCRIPTION 1.2 AX88196 B D :...............................................................................................................................4 LOCK IAGRAM 1.3 AX88196 ONNECTION 1.3.1 AX88196 Pin Connection Diagram for ISA Bus Mode.................................................................................6 1.3.2 AX88196 Pin Connection Diagram for ...

Page 3

AX88196 6.4.2 Reset Timing.............................................................................................................................................26 6.4.3 ISA Bus Access Timing..............................................................................................................................27 6.4.4 80186 Type I/O Access Timing..................................................................................................................28 6.4.5 68K Type I/O Access Timing.....................................................................................................................29 6.4.6 8051 Bus Access Timing ...........................................................................................................................30 6.4.7 MII Timing................................................................................................................................................31 6.4.8 SNI Timing................................................................................................................................................32 7.0 PACKAGE INFORMATION ...........................................................................................................................33 APPENDIX A: APPLICATION ...

Page 4

AX88196 1.0 Introduction 1.1 General Description: The AX88196 provides industrial standard NE2000 registers level compatable instruction set. Various drivers are easy acquired, maintenance and usage. No much additional effort to be paid. Software is easily port to various embedded system ...

Page 5

AX88196 1.3 AX88196 Pin Connection Diagram The AX88196 is housed in the 128-pin plastic light quad flat pack. shows the AX88196 pin connection diagram. Diagram TXD[ TXD[2] 99 TXD[3] 100 LVDD 101 CLKO 102 VSS LCLK/XTALIN 103 104 ...

Page 6

AX88196 1.3.1 AX88196 Pin Connection Diagram for ISA Bus Mode TXD[ TXD[2] 99 TXD[3] 100 LVDD 101 CLKO 102 VSS LCLK/XTALIN 103 XTALOUT 104 VSS 105 EECS 106 EECK 107 EEDI 108 EEDO 109 LOCAL CPU BUS LVDD ...

Page 7

AX88196 1.3.2 AX88196 Pin Connection Diagram for 80x86 Mode TXD[1] 97 TXD[ TXD[3] 100 LVDD 101 CLKO 102 VSS LCLK/XTALIN 103 XTALOUT 104 VSS 105 EECS 106 EECK 107 EEDI 108 EEDO 109 LOCAL CPU BUS LVDD 110 ...

Page 8

AX88196 1.3.3 AX88196 Pin Connection Diagram for MC68K Mode TXD[ TXD[2] 99 TXD[3] 100 LVDD 101 CLKO 102 VSS LCLK/XTALIN 103 104 XTALOUT VSS 105 EECS 106 EECK 107 EEDI 108 LOCAL CPU BUS EEDO 109 LVDD 110 ...

Page 9

AX88196 1.3.4 AX88196 Pin Connection Diagram for MCS-51 Mode TXD[ TXD[2] 99 TXD[3] 100 LVDD 101 CLKO 102 VSS LCLK/XTALIN 103 104 XTALOUT VSS 105 EECS 106 EECK 107 LOCAL CPU BUS EEDI 108 EEDO 109 LVDD 110 ...

Page 10

AX88196 2.0 Signal Description The following terms describe the AX88196 pin-out: All pin names with the “/” suffix are asserted low. The following abbreviations are used in following Tables. I Input O Output I/O Input/Output OD Open Drain 2.1 Local ...

Page 11

AX88196 AEN I/PD or /PSEN Tab - 1 Local CPU bus interface signals group 2.2 MII interface signals group SIGNAL TYPE PIN NO. RXD[3: – 87 CRS I RX_DV I RX_ER I RX_CLK I COL I TX_EN O ...

Page 12

AX88196 2.3 EEPROM Signals Group SIGNAL TYPE PIN NO. EECS O EECK O EEDI O EEDO I/PU Tab - 3 EEPROM bus interface signals group 2.4 SNI Interface pins group SIGNAL TYPE PIN NO. STXC I STXD O STXE O ...

Page 13

AX88196 /STRB O Tab - 5 Standard Printer Port Interface pins group 2.6 Power on configuration setup signals pins group SIGNAL TYPE PIN NO. IO_BASE[2:0] I /PU 62, 63,65 CPU[1:0] I/PU 71, 72 Tab - 6 Power on configuration setup ...

Page 14

AX88196 118, 121, 122 LVDD P 44, 54, 100, 110, HVDD P 19, 29, 64, VSS P 11, 24, 34, 40, 49,59, 69, 81,93, 102, 105, Tab - 7 Miscellaneous pins group Local CPU BUS MAC Controller Power Supply : ...

Page 15

AX88196 3.0 Memory and I/O Mapping There are four memory or I/O mapping used in AX88196. 1. EEPROM Memory Mapping 2. I/O Mapping 3. Local Memory Mapping 3.1 EEPROM Memory Mapping User can define by themselves and can access via ...

Page 16

AX88196 4.0 Registers Operation All registers of MAC Core are 8-bit wide and mapped into pages which are selected the Command Register. PAGE 0 (PS1=0,PS0=0) OFFSET 00H Command Register ( CR ) 01H Page Start Register ( ...

Page 17

AX88196 PAGE 1 (PS1=0,PS0=1) OFFSET 00H Command Register ( CR ) 01H Physical Address Register 0 ( PARA0 ) 02H Physical Address Register 1 ( PARA1 ) 03H Physical Address Register 2 ( PARA2 ) 04H Physical Address Register 3 ...

Page 18

AX88196 4.1 Command Register (CR) Offset 00H (Read/Write) FIELD NAME 7:6 PS1,PS0 PS1,PS0 : Page Select The two bit selects which register page accessed. PS1 5:3 RD2,RD1 RD2,RD1,RD0 : Remote DMA Command ,RD0 ...

Page 19

AX88196 4.3 Interrupt mask register (IMR) Offset 0FH (Write) FIELD NAME 7 - Reserved 6 RDCE DMA Complete Interrupt Enable. Default “low” disabled. 5 CNTE Counter Overflow Interrupt Enable. Default “low” disabled. 4 OVWE Overwrite Interrupt Enable. Default “low” disabled. ...

Page 20

AX88196 4.6 Transmit Status Register (TSR) Offset 04H (Read) FIELD NAME 7 OWC Out of window collision 6:4 - Reserved 3 ABT Transmit Aborted Indicates the AX88196 aborted transmission because of excessive collision. 2 COL Transmit Collided Indicates that the ...

Page 21

AX88196 4.9 Inter-frame gap (IFG) Offset 16H (Read/Write) FIELD NAME 7 - Reserved 6:0 IFG Inter-frame Gap. Default value 15H. 4.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write) FIELD NAME 7 - Reserved 6:0 IFG Inter-frame Gap Segment 1. Default ...

Page 22

AX88196 4.14 SPP Data Port Register (SPP_DPR) Offset 18H (Read/Write) FIELD NAME 7:0 DP Printer Data Port 4.15 SPP Status Port Register (SPP_SPR) Offset 19H (Read) FIELD NAME 7 /BUSY Reading a ‘0’ indicates that the printer is not ready ...

Page 23

AX88196 5.0 CPU I/O Read and Write Functions The AX88196 supports four kinds of CPU/BUS types access function, including ISA, 80186, MC68000 and MCS- 51. These Access methods are described as the following sections. 5.1 ISA bus type access functions. ...

Page 24

AX88196 5.3 MC68K CPU bus type access functions. 68K bus I/O Read function Function Mode /CS /UDS Standby Mode H X Byte Access Word Access L L 68K bus I/O Write function Function Mode /CS /UDS ...

Page 25

AX88196 6.0 Electrical Specification and Timings 6.1 Absolute Maximum Ratings Description Operating Temperature Storage Temperature Supply Voltage Supply Voltage Input Voltage Output Voltage Lead Temperature (soldering 10 seconds maximum) Note : Stress above those listed under Absolute Maximum Ratings may ...

Page 26

AX88196 6.4 A.C. Timing Characteristics 6.4.1 XTAL / CLOCK LCLK/XTALIN Tr CLKO Tod Symbol Description Tcyc CYCLE TIME Thigh CLK HIGH TIME Tlow CLK LOW TIME Tr/Tf CLK SLEW RATE Tod LCLK/XTALIN TO CLKO OUT DELAY * Note : The ...

Page 27

AX88196 6.4.3 ISA Bus Access Timing Tsu(AEN) AEN /BHE SA[9:0],SAL,SAH /IOCS16 /IOWR,/IORD Tv(RDY) RDY Read Data SD[15:0](Dout) Write Data SD[15:0](Din) Symbol Description Tsu(A) ADDRESS SETUP TIME Th(A) ADDRESS HOLD TIME Tsu(AEN) AEN SETUP TIME Th(AEN) AEN HOLD TIME Tv(CS16-A) /IOCS16 ...

Page 28

AX88196 6.4.4 80186 Type I/O Access Timing /BHE SA[9:0],SAL,SAH Tw(RW) /IOWR,/IORD Tv(RDY) RDY Read Data SD[15:0](Dout) Write Data SD[15:0](Din) Symbol Description Tsu(A) ADDRESS SETUP TIME Th(A) ADDRESS HOLD TIME Tv(RDY) RDY VALID FROM /IORD OR /IOWR Tdis(RDY) RDY DISABLE FROM ...

Page 29

AX88196 6.4.5 68K Type I/O Access Timing SA[9:1],SAL,SAH Tv(DS-WR) /UDS,/LDS (Read) R/W (Write) R/W Tv(DTACK) /DTACK (Read Data) SD[15:0](Dout) (Write Data) SD[15:0](Din) Symbol Description Tsu(A) ADDRESS SETUP TIME Th(A) ADDRESS HOLD TIME Tv(DS-WR) /UDS OR /LDS VALID FROM /W Tdis(WR-DS) ...

Page 30

AX88196 6.4.6 8051 Bus Access Timing /PSEN Tsu(PSEN) SA[9:0],SAL,SAH /IOWR,/IORD Tv(RDY) (For Reference) RDY Read Data SD[7:0](Dout) Write Data SD[7:0](Din) Symbol Description Tsu(A) ADDRESS SETUP TIME Th(A) ADDRESS HOLD TIME Tsu(PSEN) /PSEN SETUP TIME Th(PSEN) /PSEN HOLD TIME Ten(RD) OUTPUT ...

Page 31

AX88196 6.4.7 MII Timing TXCLK TXD<3:0> TXEN RXCLK RXD<3:0> RXDV RXER Symbol Description Ttclk Cycle time(100Mbps) Ttclk Cycle time(10Mbps) Ttch high time(100Mbps) Ttch high time(10Mbps) Trch low time(100Mbps) Trch low time(10Mbps) Ttv Clock to data valid Tth Data output hold ...

Page 32

AX88196 6.4.8 SNI Timing STXC STXD STXE SRXC SRXD SCRS Symbol Description Ttclk Cycle time(10Mbps) Ttch high time(10Mbps) Trch low time(10Mbps) Ttv Clock to data valid Tth Data output hold time Trclk Cycle time(10Mbps) Trch high time(10Mbps) Trcl low time(10Mbps) ...

Page 33

AX88196 7.0 Package Information pin 1 b SYMBOL Local CPU BUS MAC Controller MILIMETER MIN. NOM 0.1 1.3 1.4 0.155 0.16 13.90 14.00 13.90 14.00 0.40 ...

Page 34

AX88196 Appendix A: Application Note A.1 Using Crystal 25MHz or 20MHz AX88196 XTALIN 25MHz Crystal 8pf 2Mohm Note : The capacitors (8pf) may be various depend on the specification of crystal. While designing, please refer to the suggest circuit provided ...

Page 35

AX88196 A.4 Dual power (5V and 3.3V/3.0V) application +5V +5V HVdd +3.3V LVdd A.5 Single power (3.3V/3.0V) application +3.3V +3.3V HVdd +3.3V LVdd Local CPU BUS MAC Controller RJ45 MAGNETIC PHY/TxRx Optional EEPROM AX88196 +5V CPU I/F RJ45 MAGNETIC PHY/TxRx ...

Page 36

AX88196 A.6 Dual power (5V and 3.3V) application with 3.3V PHY The 510 and 1K Ohm resisters are just for voltage adjustment RXD[3:0] RX_DV RX_ER RX_CLK TX_EN TXD[3:0] TX_CLK MDC MDIO AX88196 Local CPU BUS MAC Controller CRS COL 510 ...

Page 37

AX88196 Errata of AX88196 Version ED2 1. SNI (Serial Network Interface) has bug for HomePNA application. Solution: Using MII interface for HomePNA solution. Refer to “Demonstration Circuit” on page 37 to 41. 2. SPP (Standard Printer Port) is fail on ...

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