AT32UC3A0128AU Atmel Corporation, AT32UC3A0128AU Datasheet - Page 198

• Manufacturer Part Number: AT32UC3A0128AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0128AU

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

AT32UC3A
23.7.3
Master Mode Operations
When configured in Master Mode, the SPI uses the internal programmable baud rate generator
as clock source. It fully controls the data transfers to and from the slave(s) connected to the SPI
bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK).
The SPI features two holding registers, the Transmit Data Register and the Receive Data Regis-
ter, and a single Shift Register. The holding registers maintain the data flow at a constant rate.
After enabling the SPI, a data transfer begins when the processor writes to the TDR (Transmit
Data Register). The written data is immediately transferred in the Shift Register and transfer on
the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line
is sampled and shifted in the Shift Register. Transmission cannot occur without reception.
Before writing the TDR, the PCS field must be set in order to select a slave.
If new data is written in TDR during the transfer, it stays in it until the current transfer is com-
pleted. Then, the received data is transferred from the Shift Register to RDR, the data in TDR is
loaded in the Shift Register and a new transfer starts.
The transfer of a data written in TDR in the Shift Register is indicated by the TDRE bit (Transmit
Data Register Empty) in the Status Register (SR). When new data is written in TDR, this bit is
cleared. The TDRE bit is used to trigger the Transmit PDC channel.
The end of transfer is indicated by the TXEMPTY flag in the SR register. If a transfer delay (DLY-
BCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of said delay.
The master clock (MCK) can be switched off at this time.
The transfer of received data from the Shift Register in RDR is indicated by the RDRF bit
(Receive Data Register Full) in the Status Register (SR). When the received data is read, the
RDRF bit is cleared.
If the RDR (Receive Data Register) has not been read before new data is received, the Overrun
Error bit (OVRES) in SR is set. When this bit is set the SPI will continue to update RDR when
data is received, overwriting the previously received data. The user has to read the status regis-
ter to clear the OVRES bit.
Figure 23-5 on page 199
shows a block diagram of the SPI when operating in Master Mode.
Fig-
ure 23-6 on page 200
shows a flow chart describing how transfers are handled.
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32058K AVR32-01/12