AT32UC3A0128AU Atmel Corporation, AT32UC3A0128AU Datasheet - Page 518

• Manufacturer Part Number: AT32UC3A0128AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0128AU

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
Figure 30-19. Abort Algorithm
30.7.2.13
30.7.2.13.1 Overview
Management of OUT Endpoints
OUT packets are sent by the host. All the data can be read by the firmware which acknowledges
or not the bank when it is empty.
The endpoint must be configured first.
The RXOUTI bit is set by hardware at the same time as FIFOCON when the current bank is full.
This triggers an EPXINT interrupt if RXOUTE = 1.
RXOUTI shall be cleared by software (by setting the RXOUTIC bit) to acknowledge the interrupt,
what has no effect on the endpoint FIFO.
The firmware then reads from the FIFO and clears the FIFOCON bit to free the bank. If the OUT
endpoint is composed of multiple banks, this also switches to the next bank. The RXOUTI and
FIFOCON bits are updated by hardware in accordance with the status of the next bank.
RXOUTI shall always be cleared before clearing FIFOCON.
The RWALL bit is set by hardware when the current bank is not empty, i.e. the software can read
further data from the FIFO.
EPRSTX = 1
TXINEC = 1
Abort Done
NBUSYBK
Endpoint
== 0?
Abort
Yes
No
Yes
KILLBKS = 1
KILLBK
== 1?
No
Disable the TXINI interrupt.
Abort is based on the fact
that no bank is busy, i.e. that
nothing has to be sent.
Kill the last written bank.
Wait for the end of the
procedure.
AT32UC3A
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