AT32UC3A0128AU Atmel Corporation, AT32UC3A0128AU Datasheet - Page 599

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AT32UC3A0128AU

Manufacturer Part Number
AT32UC3A0128AU
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3A0128AU

Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A0128AU-ALUT
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT32UC3A0128AU-U
Manufacturer:
ATMEL
Quantity:
4
32058K AVR32-01/12
• HWUPI: Host Wake-Up Interrupt Flag
Asynchronous interrupt.
Set by hardware in the following cases :
Note that this interrupt is generated even if the clock is frozen by the FRZCLK bit.
• PXINT, X in [0..6]: Pipe X Interrupt Flag
Set by hardware when an interrupt is triggered by the endpoint X (UPSTAX). This triggers a USB interrupt if the corre-
sponding pipe interrupt enable bit is set (UHINTE register). Cleared by hardware when the interrupt source is served.
• DMAXINT, X in [1..6]: DMA Channel X Interrupt Flag
Set by hardware when an interrupt is triggered by the DMA channel X. This triggers a USB interrupt if the corresponding
DMAXINTE is set (UHINTE register).
Cleared by hardware when the UHDMAX_STATUS interrupt source is cleared.
– The Host controller is in the suspend mode (SOFE=0) and an upstream resume from
– The Host controller is in the suspend mode (SOFE=0) and a Peripheral disconnection
– The Host controller is in the Idle state (VBUSRQ=0, no VBus is generated), and an
the Peripheral is detected.
is detected.
OTG SRP event initiated by the Peripheral is detected.
AT32UC3A
599

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