AT32UC3A0128AU Atmel Corporation, AT32UC3A0128AU Datasheet - Page 27
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AT32UC3A0128AU
Manufacturer Part Number
AT32UC3A0128AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A0128AU
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0128AU-U
Manufacturer:
ATMEL
Quantity:
4
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32058K AVR32-01/12
9.3.4
System registers
All interrupt levels are by default disabled when debug state is entered, but they can individually
be switched on by the monitor routine by clearing the respective mask bit in the status register.
Debug state can be entered as described in the AVR32UC Technical Reference Manual.
Debug state is exited by the retd instruction.
The system registers are placed outside of the virtual memory space, and are only accessible
using the privileged mfsr and mtsr instructions. The table below lists the system registers speci-
fied in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is
responsible for maintaining correct sequencing of any instructions following a mtsr instruction.
For detail on the system registers, refer to the AVR32UC Technical Reference Manual.
Table 9-3.
Reg #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Address
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
88
92
96
100
System Registers
JAVA_LV2
Name
SR
EVBA
ACBA
CPUCR
ECR
RSR_SUP
RSR_INT0
RSR_INT1
RSR_INT2
RSR_INT3
RSR_EX
RSR_NMI
RSR_DBG
RAR_SUP
RAR_INT0
RAR_INT1
RAR_INT2
RAR_INT3
RAR_EX
RAR_NMI
RAR_DBG
JECR
JOSP
JAVA_LV0
JAVA_LV1
Function
Status Register
Exception Vector Base Address
Application Call Base Address
CPU Control Register
Exception Cause Register
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Return Status Register for Debug Mode
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Return Address Register for Debug Mode
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
AT32UC3A
27
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