AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 213

• Manufacturer Part Number: AT32UC3A3256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.7.2
Register Name:
Access Type:
Offset:
Reset Value:
• NCSRDPULSE: NCS Pulse Length in READ Access
• NRDPULSE: NRD Pulse Length
• NCSWRPULSE: NCS Pulse Length in WRITE Access
• NWEPULSE: NWE Pulse Length
32072G–11/2011
31
23
15
–
–
–
7
–
In standard read access, the NCS signal pulse length is defined as:
The NCS pulse length must be at least one clock cycle.
In page mode read access, the NCSRDPULSE field defines the duration of the first access to one page.
In standard read access, the NRD signal pulse length is defined in clock cycles as:
The NRD pulse length must be at least one clock cycle.
In page mode read access, the NRDPULSE field defines the duration of the subsequent accesses in the page.
In write access, the NCS signal pulse length is defined as:
The NCS pulse length must be at least one clock cycle.
The NWE signal pulse length is defined as:
The NWE pulse length must be at least one clock cycle.
Pulse Register
NCS Pulse Length in write access
NCS Pulse Length in read access
30
22
14
6
PULSE
Read/Write
0x04 + CS_number*0x10
0x01010101
NWE Pulse Length
NRD Pulse Length
29
21
13
5
=
=
(
(
256 NWEPULSE 6 [ ]
256 NRDPULSE 6 [ ]
=
=
(
(
×
×
256 NCSWRPULSE 6 [ ]
256 NCSRDPULSE 6 [ ]
28
20
12
4
×
×
NCSWRPULSE
NCSRDPULSE
NWEPULSE
NRDPULSE
27
19
11
+
+
3
NRDPULSE 5:0
NWEPULSE 5:0
+
+
NCSRDPULSE 5:0
NCSWRPULSE 5:0
[
[
26
18
10
2
]
]
) clock cycles
) clock cycles
[
[
]
]
) clock cycles
) clock cycles
25
17
9
1
24
16
8
0
213