AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 868

• Manufacturer Part Number: AT32UC3A3256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 31-6. Interface mode switching sequence
31.6.4
31.6.5
32072G–11/2011
Data transfer requests
Interrupts
After the communication protocol with the Memory Stick starts, a data transfer request is
asserted to the CPU (DRQ bit in ISR) and to DMACA (internal signals), until data transfer of the
amount indicated by DSZ (CMD) is finished. However, the data transfer request stops when the
internal FIFO becomes either empty or full.
Like CPU, DMACA uses Peripheral Bus to access FIFO so it is not recommended to access MSI
registers during transfer. It is also not recommended to enable DRQ interrupt because ISR.DRQ
bit is automatically cleared when FIFO is accessed.
DMACA channel should be configured first and the data size should be a multiple of 64 bits
(FIFO size is 4 * 64bits).
The interrupt sources of MSI are :
•
•
•
•
•
•
Each interrupt source can be enabled in Interrupt Enable register (IER) and disabled in Interrupt
Disable register (IDR). The enable status is read in Interrupt Mask register (IMR). The status of
PEND : protocol command ended without error.
DRQ : data request, FIFO is full or empty.
MSINT : interrupt received from Memory Stick.
CRC : protocol ended with CRC error.
TOE : protocol ended with time out error.
CD : card detected (inserted or removed).
SET_R/W_REG_ADRS TPC
(
(
Set Parallel Interface Mode
MSSYS.SRAC=1, MSSYS.REI=1)
MSSYS.SRAC=0, MSSYS.REI=0)
Serial Interface Mode
(
WRITE_REG TPC
MSSYS.CLKDIV[7:0]=X)
system parameter
Change SCLK
(PAM bit)
OK
Error
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