AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 654

• Manufacturer Part Number: AT32UC3A3256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.7.4.2
26.7.4.3
32072G–11/2011
USB DMA Channel X Registers
(Current Transfer Descriptor)
Next Descriptor Address
Memory Area
Data Buffer 1
Data Buffer 2
Data Buffer 3
HSB Address
Control
Status
DMA Channel descriptor
Programming a chanel:
Figure 26-29. Example of DMA Chained List
The DMA channel transfer descriptor is loaded from the memory.
Be careful with the alignment of this buffer.
The structure of the DMA channel transfer descriptor is defined by three parameters as
described below:
Each DMA transfer is unidirectionnal. Direction depends on the type of the associated endpoint
(IN or OUT).
Three registers, the UDDMAnNEXTDESC, the UDDMAnADDR and UDDMAnCONTROL need
to be programmed to set up wether single or multiple transfer is used.
The following example refers to OUT endpoint. For IN endpoint, the programming is symmetric.
• Offset 0:
• Offset 4:
• Offset 8:
– The address must be aligned: 0xXXXX0
– DMA Channel n Next Descriptor Address Register: DMAnNXTDESCADDR
– The address must be aligned: 0xXXXX4
– DMA Channel n HSB Address Register: DMAnADDR
– The address must be aligned: 0xXXXX8
– DMA Channel n Control Register: DMAnCONTROL
Next Descriptor Address
Transfer Descriptor
HSB Address
Control
Next Descriptor Address
Transfer Descriptor
HSB Address
Control
Next Descriptor Address
Transfer Descriptor
HSB Address
Control
NULL
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