AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 573

• Manufacturer Part Number: AT32UC3A3256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 25-38. SPI Transfer Format (CPHA=0, 8 bits per transfer)
25.6.8.4
25.6.8.5
25.6.8.6
25.6.9
32072G–11/2011
SPI Master -> RXD
CLK cycle (for reference)
SPI Master -> TXD
SPI Master -> RTS
SPI Slave -> RXD
SPI Slave -> TXD
SPI Slave -> CTS
(CPOL= 0)
(CPOL= 1)
LIN Mode
MOSI
MISO
CLK
NSS
CLK
Receiver and Transmitter Control
Receiver Time-out
Character Transmission and Reception
See
In SPI master mode, the slave select line (NSS) is asserted low one bit period before the start of
transmission, and released high one bit period after every character transmission. A delay for at
least three bit periods is always inserted in between characters. In order to address slave
devices supporting the Chip Select Active After Transfer (CSAAT) mode, NSS can be forced low
by writing a one to the Force SPI Chip Select bit (CR.RTSEN/FCS). Releasing NSS when FCS
is one, is only possible by writing a one to the Release SPI Chip Select bit (CR.RTSDIS/RCS).
In SPI slave mode, a low level on NSS for at least one bit period will allow the slave to initiate a
transmission or reception. The Underrun Error bit (CSR.UNRE) is set if a character must be sent
while THR is empty, and TXD will be high during character transmission, as if 0xFF was being
sent. If a new character is written to THR it will be sent correctly during the next transmission
slot. Writing a one to CR.RSTSTA will clear UNRE. To ensure correct behavior of the receiver in
SPI slave mode, the master device sending the frame must ensure a minimum delay of one bit
period in between each character transmission.
Receiver Time-out’s are not possible in SPI mode as the baud rate clock is only active during
data transfers.
The USART features a LIN (Local Interconnect Network) 1.3 and 2.0 compliant mode, embed-
ding full error checking and reporting, automatic frame processing with up to 256 data bytes,
”Transmitter Operations” on page
1
MSB
MSB
2
6
6
3
5
5
4
4
4
553, and
5
”Receiver Operations” on page
3
3
6
2
2
7
1
1
8
LSB
LSB
560.
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