AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 693

• Manufacturer Part Number: AT32UC3A3256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.8.2.11
Register Name:
Access Type:
Offset:
Reset Value:
• BYCT: Byte Count
• CFGOK: Configuration OK Status
• CTRLDIR: Control Direction
• RWALL: Read/Write Allowed
32072G–11/2011
PACKET
SHORT
31
23
15
7
-
This field is set with the byte count of the FIFO.
For IN endpoints, incremented after each byte written by the software into the endpoint and decremented after each byte sent to
the host.
For OUT endpoints, incremented after each byte received from the host and decremented after each byte read by the software
from the endpoint.
This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.
This bit is updated when the ALLOC bit is written to one.
This bit is set if the endpoint n number of banks (EPBK) and size (EPSIZE) are correct compared to the maximal allowed
number of banks and size for this endpoint and to the maximal FIFO size (i.e. the DPRAM size).
If this bit is cleared, the user shall rewrite correct values to the EPBK and EPSIZE fields in the UECFGn register.
This bit is set after a SETUP packet to indicate that the following packet is an IN packet.
This bit is cleared after a SETUP packet to indicate that the following packet is an OUT packet.
Writing a zero or a one to this bit has no effect.
This bit is set for IN endpoints when the current bank is not full, i.e., the user can write further data into the FIFO.
This bit is set for OUT endpoints when the current bank is not empty, i.e., the user can read further data from the FIFO.
This bit is never set if STALLRQ is one or in case of error.
This bit is cleared otherwise.
This bit shall not be used for control endpoints.
CURRBK
Endpoint n Status Register
STALLEDI/
CRCERRI
30
22
14
6
UESTAn, n in [0..7]
Read-Only 0x0100
0x0130 + (n * 0x04)
0x00000100
BYCT
OVERFI
29
21
13
5
NBUSYBK
HBISOFLUSHI
NAKINI/
28
20
12
4
HBISOINERRI
NAKOUTI/
BYCT
27
19
11
3
-
-
ERRORTRANS
UNDERFI
RXSTPI/
CFGOK
26
18
10
2
CTRLDIR
RXOUTI
25
17
9
1
DTSEQ
RWALL
TXINI
24
16
8
0
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