AT32UC3A364S Atmel Corporation, AT32UC3A364S Datasheet - Page 546
AT32UC3A364S
Manufacturer Part Number
AT32UC3A364S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A364S
Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A364S-ALUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 546 of 1012
- Download datasheet (16Mb)
25.3
Figure 25-1. USART Block Diagram
32072G–11/2011
Block Diagram
Manager
Power
INTC
frame lengths with the time-out feature. The USART supports several operating modes, provid-
ing an interface to RS485, LIN, and SPI buses, with ISO7816 T=0 and T=1 smart card slots,
infrared transceivers, and modem port connections. Communication with slow and remote
devices is eased by the timeguard. Duplex multidrop communication is supported by address
and data differentiation through the parity bit. The hardware handshaking feature enables an
out-of-band flow control, automatically managing RTS and CTS pins. The Peripheral DMA Con-
troller connection enables memory transactions, and the USART supports chained buffer
management without processor intervention. Automatic echo, remote-, and local loopback -test
modes are also supported.
Interrupt
USART
DIV
CLK_USART
CLK_USART/DIV
USART
Peripheral bus
Channel
Peripheral DMA
Controller
Interface
User
Channel
Transmitter
BaudRate
Generator
Receiver
Modem
Signals
Control
Controller
I/O
RXD
DSR
DCD
RTS
TXD
CTS
DTR
CLK
RI
546
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