AT32UC3A364S Atmel Corporation, AT32UC3A364S Datasheet - Page 583
AT32UC3A364S
Manufacturer Part Number
AT32UC3A364S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A364S
Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A364S-ALUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 583 of 1012
- Download datasheet (16Mb)
25.6.12.1
Figure 25-51. Master Node with Peripheral DMA Controller (PDCM=0)
Figure 25-52. Master Node with Peripheral DMA Controller (PDCM=1)
32072G–11/2011
WRITE BUFFER
WRITE BUFFER
IDENTIFIER
CHKTYP
CHKDIS
PARDIS
FSDIS
DATA 0
DATA N
NACT
DLC
DATA 1
DLM
DATA 0
DATA N
|
|
|
|
|
|
|
|
Master Node Configuration
Peripheral DMA
Controller
Peripheral DMA
Controller
The Peripheral DMA Controller Mode bit (LINMR.PDCM) allows the user to select configuration:
When NACT=SUBSCRIBE, the read buffer contains the data.
• PDCM=0: LIN configuration must be written to LINMR, it is not stored in the write buffer.
• PDCM=1: LIN configuration is written by the DMA Controller to THR, and is stored in the
write buffer. Since data transfer size is a byte, the transfer is split into two accesses. The first
writes the NACT, PARDIS, CHKDIS, CHKTYP, DLM and FSDIS bits, while the second writes
the DLC field. If NACT=PUBLISH, the write buffer will also contain the Identifier.
Peripheral
RXRDY
bus
Peripheral
RXRDY
bus
NODE ACTION = PUBLISH
CONTROLLER
NODE ACTION = PUBLISH
USART LIN
CONTROLLER
USART LIN
READ BUFFER
IDENTIFIER
WRITE BUFFER
CHKTYP
PARDIS
CHKDIS
FSDIS
NACT
DATA N
DATA 0
DLM
DLC
READ BUFFER
|
|
|
|
DATA 0
DATA N
|
|
|
|
Peripheral DMA
Peripheral DMA
Controller
Controller
Peripheral
RXRDY
TXRDY
Peripheral
TXRDY
bus
RXRDY
bus
NODE ACTION = SUBSCRIBE
NODE ACTION = SUBSCRIBE
CONTROLLER
CONTROLLER
USART LIN
USART LIN
583
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