AT32UC3A364S Atmel Corporation, AT32UC3A364S Datasheet - Page 560

• Manufacturer Part Number: AT32UC3A364S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A364S

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.6.3.7
Figure 25-20. Receiver Status
25.6.3.8
32072G–11/2011
Receiver Operations
Parity
Baud Rate
RXRDY
OVRE
Clock
Read
Write
RHR
RXD
CR
When a character reception is completed, it is transferred to the Received Character field in the
Receive Holding Register (RHR.RXCHR), and the Receiver Ready bit in the Channel Status
Register (CSR.RXRDY) is set. If RXRDY is already set, RHR will be overwritten and the Overrun
Error bit (CSR.OVRE) is set. Reading RHR will clear RXRDY, and writing a one to the Reset
Status bit in the Control Register (CR.RSTSTA) will clear OVRE.
The USART supports five parity modes selected by MR.PAR. The PAR field also enables the
Multidrop mode, see
be a zero if there is an even number of ones in the data character, and if there is an odd number
it will be a one. For odd parity the reverse applies. If space or mark parity is chosen, the parity bit
will always be a zero or one, respectively. See
Table 25-7.
The receiver will report parity errors in CSR.PARE, unless parity is disabled. Writing a one to
CR.RSTSTA will clear PARE. See
Start
Alphanum
Character
Bit
D0
R
A
V
D1
D2
Parity Bit Examples
D3
0x41
0x56
0x52
Hex
D4
”Multidrop Mode” on page
D5
D6
0100 0001
0101 0010
0101 0110
D7
Parity
Bin
Bit
Figure 25-21
Stop
Bit
Start
Bit
D0
Odd
D1
1
1
0
Table
561. If even parity is selected, the parity bit will
D2
D3
25-7.
D4
Even
0
0
1
D5
D6
Parity Mode
D7
Mark
Parity
Bit
1
1
1
Stop
Bit
Space
RSTSTA = 1
0
0
0
None
-
-
-
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