AT32UC3A4256 Atmel Corporation, AT32UC3A4256 Datasheet - Page 188

• Manufacturer Part Number: AT32UC3A4256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4256

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32072G–11/2011
•Write cycle
Figure 15-11. Write Cycle
The write cycle time is defined as the total duration of the write cycle, that is, from the time where
address is set on the address bus to the point where address may change. The total write cycle
time is equal to:
Similarly,
All NWE and NCS (write) timings are defined separately for each chip select as an integer num-
ber of CLK_SMC cycles. To ensure that the NWE and NCS timings are coherent, the user must
define the total write cycle instead of the hold timing. This implicitly defines the NWE hold time
and NCS (write) hold times as:
And,
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
CLK_SMC
NWE
NCS
NWECYCLE
NCSWRHOLD
NCSWRSETUP
NWECYCLE
NWEHOLD
NWESETUP
=
=
NCSWRSETUP
=
=
NWECYCLE NCSWRSETUP
NWECYCLE NWESETUP
NWESETUP
NCSWRPULSE
NWEPULSE
NWECYCLE
–
+
–
+
NCSWRPULSE
NWEPULSE
–
+
–
NWEPULSE
+
NWEHOLD
NCSWRPULSE
NCSWRHOLD
NWEHOLD
NCSWRHOLD
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