AT32UC3A4256 Atmel Corporation, AT32UC3A4256 Datasheet - Page 644
AT32UC3A4256
Manufacturer Part Number
AT32UC3A4256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4256
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A4256S-C1UR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3A4256S-U
Manufacturer:
ST
Quantity:
79
Part Number:
AT32UC3A4256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 644 of 1012
- Download datasheet (16Mb)
26.7.2.20
32072G–11/2011
Test Modes
•DMA interrupts
The processing device DMA interrupts are:
There is no exception device DMA interrupt.
When written to one, the UDCON.TSTPCKT bit switches the USB device controller in a “test
packet”mode:
The transceiver repeatedly transmit the packet stored in the current bank. TSTPCKT must be
written to zero to exit the “test-packet” mode. The endpoint shall be reset by software after a
“test-packet” mode.
This enables the testing of rise and falling times, eye patterns, jitter, and any other dynamic
waveform specifications.
The flow control used to send the packets is as follows:
To stop the test-packet mode, just write a zero to the TSTPCKT bit.
• The NAKed OUT Interrupt (NAKOUTI)
• The High-bandwidth isochronous IN error Interrupt (HBISOINERRI) if the high-bandwidth
• The NAKed IN Interrupt (NAKINI)
• The High-bandwidth isochronous IN Flush error Interrupt (HBISOFLUSHI) if the high-
• The Overflow Interrupt (OVERFI)
• The STALLed Interrupt (STALLEDI)
• The CRC Error Interrupt (CRCERRI)
• The Transaction error (ERRORTRANS) interrupt if the high-bandwidth isochronous feature is
• The End of USB Transfer Status (EOTSTA) interrupt
• The End of Channel Buffer Status (EOCHBUFFSTA) interrupt
• The Descriptor Loaded Status (DESCLDSTA) interrupt
• TSTPCKT=1;
• Store data in an endpoint bank
• Write a zero to FifoCON bit
isochronous feature is supported by the device (see the UFEATURES register for this)
bandwidth isochronous feature is supported by the device (see the UFEATURES register for
this)
supported by the device (see the UFEATURES register for this)
644
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