AT32UC3A4256 Atmel Corporation, AT32UC3A4256 Datasheet - Page 530
AT32UC3A4256
Manufacturer Part Number
AT32UC3A4256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4256
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A4256S-C1UR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3A4256S-U
Manufacturer:
ST
Quantity:
79
Part Number:
AT32UC3A4256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 530 of 1012
- Download datasheet (16Mb)
24.9.5
Name:
Access Type:
Offset:
Reset value:
• PERIOD: Transmit Period Divider Selection
• STTDLY: Transmit Start Delay
• START: Transmit Start Selection
32072G–11/2011
31
23
15
7
-
START
Others
This field selects the divider to apply to the selected transmit clock in order to generate a periodic Frame Sync Signal.
If equal to zero, no signal is generated.
If not equal to zero, a signal is generated each 2 x (PERIOD+1) transmit clock periods.
If STTDLY is not zero, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission.
When the transmitter is programmed to start synchronously with the receiver, the delay is also applied.
Note: STTDLY must be written carefully, in relation to Transmit Sync Data transmission.
0
1
2
3
4
5
6
7
Transmit Clock Mode Register
CKG
30
22
14
6
-
TCMR
Read/Write
0x18
0x00000000
Transmit Start
Continuous, as soon as a word is written to the THR Register (if Transmit is enabled), and
immediately after the end of transfer of the previous data.
Receive start
Detection of a low level on TX_FRAME_SYNC signal
Detection of a high level on TX_FRAME_SYNC signal
Detection of a falling edge on TX_FRAME_SYNC signal
Detection of a rising edge on TX_FRAME_SYNC signal
Detection of any level change on TX_FRAME_SYNC signal
Detection of any edge on TX_FRAME_SYNC signal
Reserved
CKI
29
21
13
5
-
28
20
12
4
-
PERIOD
STTDLY
CKO
27
19
11
3
26
18
10
2
START
25
17
9
1
CKS
24
16
8
0
530
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