AT32UC3A4256 Atmel Corporation, AT32UC3A4256 Datasheet - Page 511
AT32UC3A4256
Manufacturer Part Number
AT32UC3A4256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4256
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A4256S-C1UR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3A4256S-U
Manufacturer:
ST
Quantity:
79
Part Number:
AT32UC3A4256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 511 of 1012
- Download datasheet (16Mb)
24.7.1.1
24.7.1.2
32072G–11/2011
Clock divider
Transmitter clock management
Figure 24-4. Divided Clock Block Diagram
The peripheral clock divider is determined by the 12-bit Clock Divider field (its maximal value is
4095) in the Clock Mode Register (CMR.DIV), allowing a peripheral clock division by up to 8190.
The divided clock is provided to both the receiver and transmitter. When this field is written to
zero, the clock divider is not used and remains inactive.
When CMR.DIV is written to a value equal to or greater than one, the divided clock has a fre-
quency of CLK_SSC divided by two times CMR.DIV. Each level of the divided clock has a
duration of the peripheral clock multiplied by CMR.DIV. This ensures a 50% duty cycle for the
divided clock regardless of whether the CMR.DIV value is even or odd.
Figure 24-5.
Table 24-2.
The transmitter clock is generated from the receiver clock, the divider clock, or an external clock
scanned on the TX_CLOCK pin. The transmitter clock is selected by writing to the Transmit
Clock Selection field in the Transmit Clock Mode Register (TCMR.CKS). The transmit clock can
Maximum
CLK_SSC / 2
Divided Clock
Divided Clock
Range of Clock Divider
CLK_SSC
CLK_SSC
Divided Clock Generation
DIV = 3
DIV = 1
CLK_SSC
/ 2
Divided Clock Frequency = CLK_SSC/2
Divided Clock Frequency = CLK_SSC/6
Clock Divider
12-bit Counter
Minimum
CLK_SSC / 8190
CMR
Divided Clock
511
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