AT32UC3A4256 Atmel Corporation, AT32UC3A4256 Datasheet - Page 852
AT32UC3A4256
Manufacturer Part Number
AT32UC3A4256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4256
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A4256S-C1UR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3A4256S-U
Manufacturer:
ST
Quantity:
79
Part Number:
AT32UC3A4256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 852 of 1012
- Download datasheet (16Mb)
• DTIP: Data Transfer in Progress
• BLKE: Data Block Ended
• TXRDY: Transmit Ready
• RXRDY: Receiver Ready
• CMDRDY: Command Ready
32072G–11/2011
A block write operation uses a simple busy signalling of the write operation duration on the data (DAT[0]) line: during a data
transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line
(DAT[0]) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer
block length becomes free.
The NOTBUSY bit allows to deal with these different states.
1: MCI is ready for new data transfer.
0: MCI is not ready for new data transfer.
This bit is cleared at the end of the card response.
This bit is set when the busy state on the data line is ended. This corresponds to a free internal data receive buffer of the card.
Refer to the MMC or SD Specification for more details concerning the busy behavior.
This bit is set when the current data transfer is in progress.
This bit is cleared at the end of the CRC16 calculation
1: The current data transfer is still in progress.
0: No data transfer in progress.
This bit must be used only for Write Operations.
This bit is set when a data block transfer has ended.
This bit is cleared when reading SR.
1: a data block transfer has ended, including the CRC16 Status transmission, the bit is set for each transmitted CRC Status.
0: A data block transfer is not yet finished.
Refer to the MMC or SD Specification for more details concerning the CRC Status.
This bit is set when the last data written in the TDR register has been transferred.
This bit is cleared the last data written in the TDR register has not yet been transferred.
This bit is set when the data has been received since the last read of the RDR register.
This bit is cleared when the data has not yet been received since the last read of the RDR register.
This bit is set when the last command has been sent.
This bit is cleared when writing the CMDR register
852
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