AT32UC3A464 Atmel Corporation, AT32UC3A464 Datasheet - Page 609
AT32UC3A464
Manufacturer Part Number
AT32UC3A464
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A464
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Price
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Part Number:
AT32UC3A464-CIUT
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ATMEL
Quantity:
180
Part Number:
AT32UC3A464-CIUT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3A464-U
Manufacturer:
XILINX
Quantity:
1
Company:
Part Number:
AT32UC3A464S-U
Manufacturer:
ATMEL
Quantity:
551
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 609 of 1012
- Download datasheet (16Mb)
25.7.16
Name:
Access Type:
Offset:
Reset Value:
• PDCM: Peripheral DMA Controller Mode
• DLC: Data Length Control
• WKUPTYP: Wakeup Signal Type
• FSDIS: Frame Slot Mode Disable
• DLM: Data Length Mode
• CHKTYP: Checksum Type
• CHKDIS: Checksum Disable
• PARDIS: Parity Disable
• NACT: LIN Node Action
Table 25-26.
32072G–11/2011
WKUPTYP
0
31
23
15
–
–
7
0: The LIN mode register is not written by the Peripheral DMA Controller.
1: The LIN mode register is, except for this bit, written by the Peripheral DMA Controller.
0 - 255: If DLM=0 this field defines the response data length to DLC+1 bytes.
0: Writing a one to CR.LINWKUP will send a LIN 2.0 wakeup signal.
1: Writing a one to CR.LINWKUP will send a LIN 1.3 wakeup signal.
0: The Frame Slot mode is enabled.
1: The Frame Slot mode is disabled.
0: The response data length is defined by DLC.
1: The response data length is defined by bits 4 and 5 of the Identifier (LINIR.IDCHR).
0: LIN 2.0 “Enhanced” checksum
1: LIN 1.3 “Classic” checksum
0: Checksum is automatically computed and sent when master, and checked when slave.
1: Checksum is not computed and sent, nor checked.
0: Identifier parity is automatically computed and sent when master, and checked when slave.
1: Identifier parity is not computed and sent, nor checked.
NACT
LIN Mode Register
0
FSDIS
30
22
14
LINMR
Read-write
0x54
0x00000000
–
–
6
Mode Description
PUBLISH: The USART transmits the response.
DLM
29
21
13
–
–
5
CHKTYP
28
20
12
–
–
4
DLC
CHKDIS
27
19
11
–
–
3
PARDIS
26
18
10
–
–
2
25
17
–
–
9
1
NACT
PDCM
24
16
–
8
0
609
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