AT32UC3A464 Atmel Corporation, AT32UC3A464 Datasheet - Page 829
AT32UC3A464
Manufacturer Part Number
AT32UC3A464
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A464
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A464-CIUT
Manufacturer:
ATMEL
Quantity:
180
Part Number:
AT32UC3A464-CIUT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3A464-U
Manufacturer:
XILINX
Quantity:
1
Company:
Part Number:
AT32UC3A464S-U
Manufacturer:
ATMEL
Quantity:
551
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 829 of 1012
- Download datasheet (16Mb)
30.6.4.1
30.6.4.2
30.6.4.3
32072G–11/2011
WRITE_MULTIPLE_BLOCK
WRITE_SINGLE_BLOCK operation using DMA Controller
READ_SINGLE_BLOCK operation using DMA Controller
1. Wait until the current command execution has successfully terminated.
2. Write the block length in the card. This value defines the value block_lenght.
3. Write the MR.BLKLEN with block_lenght value.
4. Configure the DMA Channel in the DMA Controller.
5. Write the DMA register with the following fields:
6. Write a one to the DMA Transfer done bit in IER register (IER.DMADONE).
7. Issue a WRITE_SINGLE_BLOCK command.
8. Wait for DMA Transfer done bit in SR register (SR.DMADONE) is set.
1. Wait until the current command execution has successfully terminated.
2. Write the block length in the card. This value defines the value block_lenght.
3. Write the MR.BLKLEN with block_lenght value.
4. Configure the DMA Channel in the DMA Controller.
5. Write the DMA register with the following fields:
6. Write a one to the IER.DMADONE bit.
7. Issue a READ_SINGLE_BLOCK command.
8. Wait for SR.DMADONE bit is set.
1. Wait until the current command execution has successfully terminated.
2. Write the block length in the card. This value defines the value block_lenght.
3. Write the MR.BLKLEN with block_lenght value.
4. Program the DMA Controller to use a list of descriptors. Each descriptor transfers one
5. Program the DMA register with the following fields:
6. Write a one to the IER.DMADONE bit.
7. Issue a WRITE_MULTIPLE_BLOCK command.
8. Wait for DMA chained buffer transfer complete interrupt.
c. Check that the Transfer Done bit in the SR register (SR.XFRDONE) is set
– Write the dma_offset to the DMA Write Buffer Offset field (DMA.OFFSET).
– Write the DMA Channel Read and Write Chunk Size field (DMA.CHKSIZE).
– Write a one to he DMA.DMAEN bit to enable DMA hardware handshaking in the
d. Check that the SR.XFRDONE bit is set.
– Write zero to the DMA.OFFSET field.
– Write the DMA.CHKSIZE field.
– Write to one the DMA.DMAEN bit to enable DMA hardware handshaking in the MCI.
a. Check that the SR.XFRDONE bit is set.
block of data.
– Write the dma_offset in the DMA.OFFSET field.
– Write the DMA.CHKSIZE field.
– Write a one to the DMA.DMAEN bit to enable DMA hardware handshaking in the
MCI.
MCI.
829
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