AT32UC3C2128C Atmel Corporation, AT32UC3C2128C Datasheet - Page 351
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AT32UC3C2128C
Manufacturer Part Number
AT32UC3C2128C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C2128C
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C2128C-A2UR
Manufacturer:
ATMEL
Quantity:
1 043
Part Number:
AT32UC3C2128C-Z2UR
Manufacturer:
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19.6.3
19.6.4
19.7
19.7.1
32117C–AVR-08/11
Functional Description
Clocks
Interrupts
SDRAM Device Initialization
The clock for the SDRAMC bus interface (CLK_SDRAMC) is generated by the Power Manager.
This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the SDRAMC before disabling the clock, to avoid freezing the SDRAMC in an undefined
state.
The SDRAMC interrupt request line is connected to the interrupt controller. Using the SDRAMC
interrupt requires the interrupt controller to be programmed first.
The initialization sequence is generated by software. The SDRAM devices are initialized by the
following sequence:
1. SDRAM features must be defined in the CR register by writing the following fields with
2. For mobile SDRAM devices, Temperature Compensated Self Refresh (TCSR), Drive
3. The Memory Device Type field must be defined in the Memory Device Register
4. A No Operation (NOP) command must be issued to the SDRAM devices to start the
5. A minimum pause of 200µs is provided to precede any signal toggle.
6. An All Banks Precharge command must be issued to the SDRAM devices. The user
7. Eight Auto Refresh commands are provided. The user must write the value four to the
8. A Load Mode Register command must be issued to program the parameters of the
9. For mobile SDRAM initialization, an Extended Load Mode Register command must be
10. The user must go into Normal Mode, writing the value 0 to the MR.MODE field and per-
11. Write the refresh rate into the Refresh Timer Count field in the Refresh Timer Register
the desired value: asynchronous timings (TXSR, TRAS, TRCD, TRP, TRC, and TWR),
Number of Columns (NC), Number of Rows (NR), Number of Banks (NB), CAS Latency
(CAS), and the Data Bus Width (DBW).
Strength (DS) and Partial Array Self Refresh (PASR) fields must be defined in the Low
Power Register (LPR).
(MDR.MD).
SDRAM clock. The user must write the value one to the Command Mode field in the
SDRAMC Mode Register (MR.MODE) and perform a write access to any SDRAM
address.
must write the value two to the MR.MODE field and perform a write access to any
SDRAM address.
MR.MODE field and performs a write access to any SDRAM location eight times.
SDRAM devices in its Mode Register, in particular CAS latency, burst type, and burst
length. The user must write the value three to the MR.MODE field and perform a write
access to the SDRAM. The write address must be chosen so that BA[1:0] are set to
zero. See
issued to program the SDRAM devices parameters (TCSR, PASR, DS). The user must
write the value five to the MR.MODE field and perform a write access to the SDRAM.
The write address must be chosen so that BA[1] or BA[0] are equal to one. See
19.8.1
forming a write access at any location in the SDRAM.
(TR.COUNT). The refresh rate is the delay between two successive refresh cycles. The
SDRAM device requires a refresh every 15.625µs or 7.81µs. With a 100MHz fre-
for details about Extended Load Mode Register command.
Section 19.8.1
for details about Load Mode Register command.
AT32UC3C
Section
351
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