AT32UC3C2128C Atmel Corporation, AT32UC3C2128C Datasheet - Page 983
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AT32UC3C2128C
Manufacturer Part Number
AT32UC3C2128C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C2128C
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C2128C-A2UR
Manufacturer:
ATMEL
Quantity:
1 043
Part Number:
AT32UC3C2128C-Z2UR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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33.6.2.10
32117C–AVR-08/11
Method 3: Automatic write of duty-cycle values and automatic trigger of the update
In this mode, the update of the duty cycle values is made automatically by the Peripheral DMA
Controller (PDCA). The update of the period value, the dead-time values and the update period
value must be made by writing in their respective update registers with the CPU (respectively
CPRDUPDx, DTUPDx and SCUPUPD).
To trigger the update of the period value and the dead-time values, the user must use the
UPDULOCK bit which allows to update synchronously (at the same PWM period) the synchro-
nous channels:
After writing the UPDULOCK bit to one, it is held at this value until the update occurs, then it is
read 0.
The update of the duty-cycle values and the update period value is triggered automatically after
an update period.
To configure the automatic update, the user must define a value for the Update Period by the
UPR field in the
troller waits UPR+1 periods of synchronous channels before updating automatically the duty
values and the update period value.
Using the PDCA removes processor overhead by reducing its intervention during the transfer.
This significantly reduces the number of clock cycles required for a data transfer, which
improves micro controller performance.
The PDCA must write the duty-cycle values in the synchronous channels index order. For exam-
ple if the channels 0, 1 and 3 are synchronous channels, the PDCA must write the duty-cycle of
the channel 0 first, then the duty-cycle of the channel 1, and finally the duty-cycle of the channel
3.
The following status are reported in the
Depending on the interrupt mask in the IMR2 register, an interrupt can be generated by these
bits.
• If the UPDULOCK bit is set to 1, the update is done at the next PWM period of the
• If the UPDULOCK bit is not set to 1, the update is locked and cannot be performed.
• WRDY: this bit is set to 1 when the PWM Controller is ready to receive new duty-cycle values
• UNRE: this bit is set to 1 when the update period defined by the UPR field is elapsed while
synchronous channels.
and a new update period value. It is reset to 0 when the ISR2 register is read. The user can
choose to synchronize the WRDY bit and the PDCA transfer request with a comparison
match (see
register.
the whole data has not been written by the PDCA. It is reset to 0 when the ISR2 register is
read.
Section 33.6.3 on page
”Sync Channels Update Period Register” on page 1008
986), by the PTRM and PTRCS fields in the SCM
”Interrupt Status Register 2” on page 1013
(SCUP). The PWM con-
AT32UC3C
(ISR2):
983
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