AT32UC3C2128C Atmel Corporation, AT32UC3C2128C Datasheet - Page 363
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AT32UC3C2128C
Manufacturer Part Number
AT32UC3C2128C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C2128C
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C2128C-A2UR
Manufacturer:
ATMEL
Quantity:
1 043
Part Number:
AT32UC3C2128C-Z2UR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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- Download datasheet (20Mb)
19.8.3
Register Name:
Access Type:
Offset:
Reset Value:
• TXSR: Exit Self Refresh to Active Delay
• TRAS: Active to Precharge Delay
• TRCD: Row to Column Delay
• TRP: Row Precharge Delay
• TRC: Row Cycle Delay
• TWR: Write Recovery Delay
• DBW: Data Bus Width
32117C–AVR-08/11
DBW
31
23
15
7
Reset value is eight cycles.
This field defines the delay between SCKE set high and an Activate command in number of cycles. Number of cycles is between
0 and 15.
Reset value is five cycles.
This field defines the delay between an Activate command and a Precharge command in number of cycles. Number of cycles is
between 0 and 15.
Reset value is two cycles.
This field defines the delay between an Activate command and a Read/Write command in number of cycles. Number of cycles
is between 0 and 15.
Reset value is three cycles.
This field defines the delay between a Precharge command and another command in number of cycles. Number of cycles is
between 0 and 15.
Reset value is seven cycles.
This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is between 0
and 15.
Reset value is two cycles.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15.
Reset value is 16 bits.
0: Reserved.
1: Data bus width is 16 bits.
Configuration Register
30
22
14
6
CR
Read/Write
0x08
0x852372C0
TRCD
TXSR
TRC
CAS
29
21
13
5
NB
28
20
12
4
27
19
11
3
NR
26
18
10
2
TRAS
TWR
TRP
25
17
9
1
AT32UC3C
NC
24
16
8
0
363
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