AT32UC3C2128C Atmel Corporation, AT32UC3C2128C Datasheet - Page 765
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AT32UC3C2128C
Manufacturer Part Number
AT32UC3C2128C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C2128C
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C2128C-A2UR
Manufacturer:
ATMEL
Quantity:
1 043
Part Number:
AT32UC3C2128C-Z2UR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
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- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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29.6.1.5
29.6.2
29.6.2.1
29.6.2.2
32117C–AVR-08/11
Channel Handling
Memory pointer
Initialization
Enabling / Disabling
When Overrun Mode is enabled, the MOb is not disabled after a successful reception. Overrun
Mode is enabled by writing a one to CANCFG.OVRM. The Overwrite bit in the MOb Status Reg-
ister (MObSR.OVW) is set if a previously received message has been overwritten.
The mode configured by CANCFG.OVRM is used by all MObs configured for reception.
Each channel uses a section of RAM for storing messages. User must allocate RAM space for
the channels and store the base address of this space into the Channel RAM Base Address
Register (CANRAMB). Four words per MOb in use must be allocated.
Channels operate independently so the allocated memory spaces do not need to be consecu-
tive. Make sure that the memory spaces do not overlap.
CAN channels are initialized by writing a one to the Initialization bit in the Control Register
(CANCTRL.INIT).
Initialization resets all internal state machines and clears all user interface registers except CAN-
RAMB, CANCFG and CANCTRL.INIT.
CANCTRL.INIT should not be cleared until the channel has been disabled. The channel is dis-
abled by writing the Channel Enable bit (CANCTRL.CEN) to zero. When the Channel Enable
status bit (CANSR.CEN) is zero, the channel has been disabled and CANCTRL.INIT can be
written to zero. Thereafter the channel can be restarted by writing a one to CANCTRL.CEN. See
Figure 29-4
It is not possible to write to other CANCTRL bits when CANCTRL.INIT is one. User must write a
zero to CANCTRL.INIT before writing a new value to CANCTRL.
Figure 29-4. Initialization Sequence
Note: Initialization requires all clocks to be running.
A channel is enabled and ready to communicate on the bus when it has detected a bus idle con-
dition (i.e. 11 consecutive recessive bits).
The channel is enabled by writing a one to CANCTRL.CEN and disabled by writing a zero to this
bit. The enable status of channel can be read in CANSR.CES bit.
for details.
CANCTRL.CEN
CANCTRL.INIT
CANSR.CES
init. request
(user write)
release init.
(user write)
(user write)
restart
AT32UC3C
765
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