AT32UC3C2128C Atmel Corporation, AT32UC3C2128C Datasheet - Page 43
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AT32UC3C2128C
Manufacturer Part Number
AT32UC3C2128C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C2128C
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C2128C-A2UR
Manufacturer:
ATMEL
Quantity:
1 043
Part Number:
AT32UC3C2128C-Z2UR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
- Current page: 43 of 1313
- Download datasheet (20Mb)
Table 5-3.
5.4
32117C–AVR-08/11
CPU Local Bus Mapping
Peripheral Address Mapping
0xFFFF3C00
0xFFFF4C00
0xFFFF5C00
0xFFFF6C00
0xFFFF3800
0xFFFF4000
0xFFFF4400
0xFFFF4800
0xFFFF5000
0xFFFF5400
0xFFFF5800
0xFFFF6000
0xFFFF6400
0xFFFF6800
0xFFFF7000
Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to
being mapped on the Peripheral Bus. These registers can therefore be reached both by
accesses on the Peripheral Bus, and by accesses on the local bus.
Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since
the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at
CPU speed, one write or read operation can be performed per clock cycle to the local bus-
mapped GPIO registers.
DACIFB0
DACIFB1
QDEC0
QDEC1
ACIFA0
ACIFA1
TWIM0
TWIM1
TWIS0
TWIS1
PEVC
PWM
IISC
TC1
AW
Inter-IC Sound (I2S) Controller - IISC
Two-wire Master Interface - TWIM0
Two-wire Master Interface - TWIM1
Two-wire Slave Interface - TWIS0
Two-wire Slave Interface - TWIS1
Pulse Width Modulation Controller - PWM
Quadrature Decoder - QDEC0
Quadrature Decoder - QDEC1
Timer/Counter - TC1
Peripheral Event Controller - PEVC
Analog Comparators Interface - ACIFA0
Analog Comparators Interface - ACIFA1
DAC interface - DACIFB0
DAC interface - DACIFB1
aWire - AW
AT32UC3C
43
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