AT89C51AC3 Atmel Corporation, AT89C51AC3 Datasheet - Page 40

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AT89C51AC3

Manufacturer Part Number
AT89C51AC3
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT89C51AC3

Flash (kbytes)
64 Kbytes
Max. Operating Frequency
60 MHz
Cpu
8051-12C
Max I/o Pins
32
Spi
1
Uart
1
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
62.5
Sram (kbytes)
2.25
Eeprom (bytes)
2048
Self Program Memory
API
Operating Voltage (vcc)
3.0 to 5.5
Timers
4
Isp
UART
Watchdog
Yes

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Figure 22. External Code Fetch Waveforms
Flash Memory
Architecture
Figure 23. Flash Memory Architecture with ENBOOT=1 (boot mode)
40
AT89C51AC3
Extra Row (128 Bytes)
Hardware Security (1 byte)
Column Latches (128 Bytes)
CPU Clock
PSEN#
ALE
P0
P2
D7:0
PCH
AT89C51AC3 features two on-chip Flash memories:
The FM0 can be program by both parallel programming and Serial In-System Program-
ming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP
mode is detailed in the "In-System Programming" section.
All Read/Write access operations on Flash Memory by user application are managed by
a set of API described in the "In-System Programming" section.
The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh. Figure
23 and Figure 24 show the Flash memory configuration with ENBOOT=1 and
ENBOOT=0.
FFFFh
F800h
0000h
Flash memory FM0:
containing 64K Bytes of program memory (user space) organized into 128 byte
pages,
Flash memory FM1:
2K Bytes for boot loader and Application Programming Interfaces (API).
PCL
64K Bytes
FM0
PCH
Memory space not accessible
D7:0
FM1 mapped between FFFFh and
F800h when bit ENBOOT is set in
AUXR1 register
PCL
Flash memory
boot space
2K Bytes
FM1
PCH
D7:0
FFFFh
F800h
4383D–8051–02/08

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