AT89C51AC3 Atmel Corporation, AT89C51AC3 Datasheet - Page 83

• Manufacturer Part Number: AT89C51AC3
• Manufacturer: Atmel Corporation

Specifications of AT89C51AC3

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 32
• Spi: 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 2.25
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART
• Watchdog: Yes

Serial Port Interface
(SPI)
Features
Signal Description
Master Output Slave Input
(MOSI)
Master Input Slave Output
(MISO)
SPI Serial Clock (SCK)
Slave Select (SS)
4383D–8051–02/08
The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial
communication between the MCU and peripheral devices, including other MCUs.
Features of the SPI Module include the following:
•
•
•
•
•
Figure 43 shows a typical SPI bus configuration using one Master controller and many
Slave peripherals. The bus is made of three wires connecting all the devices.
Figure 43. SPI Master/Slaves Interconnection
The Master device selects the individual Slave devices by using four pins of a parallel
port to control the four SS pins of the Slave devices.
This 1-bit signal is directly connected between the Master Device and a Slave Device.
The MOSI line is used to transfer data in series from the Master to the Slave. Therefore,
it is an output signal from the Master, and an input signal to a Slave. A Byte (8-bit word)
is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
This 1-bit signal is directly connected between the Slave Device and a Master Device.
The MISO line is used to transfer data in series from the Slave to the Master. Therefore,
it is an output signal from the Slave, and an input signal to the Master. A Byte (8-bit
word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
This signal is used to synchronize the data transmission both in and out of the devices
through their MOSI and MISO lines. It is driven by the Master for eight clock cycles
which allows to exchange one Byte on the serial lines.
Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay
low for any message for a Slave. It is obvious that only one Master (SS high level) can
drive the network. The Master may select each Slave device by software through port
pins (Figure 44). To prevent bus conflicts on the MISO line, only one slave should be
selected at a time by the Master for a transmission.
Full-duplex, three-wire synchronous transfers
Master or Slave operation
Six programmable Master clock rates in master mode
Serial clock with programmable polarity and phase
Master Mode fault error flag with MCU interrupt capability
Master
Slave 4
MISO
MOSI
SCK
SS
0
1
2
3
VDD
Slave 3
Slave 1
Slave 2
83