AT89C51AC3 Atmel Corporation, AT89C51AC3 Datasheet - Page 70
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AT89C51AC3
Manufacturer Part Number
AT89C51AC3
Description
Manufacturer
Atmel Corporation
Specifications of AT89C51AC3
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
60 MHz
Cpu
8051-12C
Max I/o Pins
32
Spi
1
Uart
1
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
62.5
Sram (kbytes)
2.25
Eeprom (bytes)
2048
Self Program Memory
API
Operating Voltage (vcc)
3.0 to 5.5
Timers
4
Isp
UART
Watchdog
Yes
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Part Number
Manufacturer
Quantity
Price
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Part Number:
AT89C51AC3-SLSIM
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Interrupt
Registers
70
AT89C51AC3
Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This
flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer
interrupt routine. Interrupts are enabled by setting
interrupts are globally enabled by setting EA bit in IEN0 register.
Figure 39. Timer Interrupt System
Table 30. TCON Register
TCON (S:88h)
Timer/Counter Control Register
Reset Value = 0000 0000b
Number
TF1
Bit
7
7
6
5
4
3
2
1
0
Mnemonic Description
TR1
TR1
TR0
TF1
TF0
Bit
IE1
IT1
IE0
IT0
6
TCON.5
TCON.7
TF0
TF1
Timer 1 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.
Timer 1 Run Control Bit
Clear to turn off Timer/Counter 1.
Set to turn on Timer/Counter 1.
Timer 0 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.
Timer 0 Run Control Bit
Clear to turn off Timer/Counter 0.
Set to turn on Timer/Counter 0.
Interrupt 1 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (see IT1).
Set by hardware when external interrupt is detected on INT1# pin.
Interrupt 1 Type Control Bit
Clear to select low level active (level triggered) for external interrupt 1 (INT1#).
Set to select falling edge active (edge triggered) for external interrupt 1.
Interrupt 0 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (see IT0).
Set by hardware when external interrupt is detected on INT0# pin.
Interrupt 0 Type Control Bit
Clear to select low level active (level triggered) for external interrupt 0 (INT0#).
Set to select falling edge active (edge triggered) for external interrupt 0.
TF0
5
TR0
4
IEN0.1
IEN0.3
ET0
ET1
IE1
3
ETx
Timer 0
Interrupt Request
Timer 1
Interrupt Request
bit in IEN0 register. This assumes
IT1
2
4383D–8051–02/08
IE0
1
IT0
0