AT89C51ED2 Atmel Corporation, AT89C51ED2 Datasheet - Page 84
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AT89C51ED2
Manufacturer Part Number
AT89C51ED2
Description
Manufacturer
Atmel Corporation
Specifications of AT89C51ED2
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
60 MHz
Cpu
8051-12C
Max I/o Pins
32
Spi
1
Uart
1
Sram (kbytes)
2
Eeprom (bytes)
2048
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 5.5
Timers
4
Isp
UART
Watchdog
Yes
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19. Hardware Watchdog Timer
19.1
84
Using the WDT
AT89C51RD2/ED2
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upset. The WDT consists of a 14-bit counter and the Watchdog Timer ReSeT
(WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user
must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is
enabled, it will increment every machine cycle while the oscillator is running and there is no way
to disable the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin.
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR loca-
tion 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to
WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH)
and this will reset the device. When WDT is enabled, it will increment every machine cycle while
the oscillator is running. This means the user must reset the WDT at least every 16383 machine
cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write
only register. The WDT counter cannot be read or written. When WDT overflows, it will generate
an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x T
T
tions of code that will periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 2
ranking from 16 ms to 2s @ F
description,
sequence, and can not be modified until next reset.
Table 19-1.
WDTRST - Watchdog Reset Register (0A6h)
Reset Value = XXXX XXXXb
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.
CLK PERIPH
7
-
= 1/F
Table
WDTRST Register
CLK PERIPH
6
-
19-1. The WDTPRG register should be configured before the WDT activation
. To make the best use of the WDT, it should be serviced in those sec-
5
OSCA
-
= 12 MHz. To manage this feature, refer to WDTPRG register
7
counter has been added to extend the Time-out capability,
4
-
3
-
2
-
1
-
CLK PERIPH
4235K–8051–05/08
, where
0
-