AT89C51RE2 Atmel Corporation, AT89C51RE2 Datasheet - Page 156

• Manufacturer Part Number: AT89C51RE2
• Manufacturer: Atmel Corporation

Specifications of AT89C51RE2

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Spi: 1
• Uart: 2
• Sram (kbytes): 8.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART/OCD
• Watchdog: Yes

OverRun Condition
Interrupts
156
AT89C51RE2
Figure 64. Mode Fault Conditions in Slave Mode
Note:
This error mean that the speed is not adapted for the running application:
An OverRun condition occurs when a byte has been received whereas the previous one has not
been read by the application yet.
The last byte (which generate the overrun error) does not overwrite the unread data so that it
can still be read. Therefore, an overrun error always indicates the loss of data.
Three SPI status flags can generate a CPU interrupt requests:
Table 114. SPI Interrupts
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been
completed. SPIF bit generates transmitter CPU interrupt request only when SPTEIE is disabled.
Mode Fault flag, MODF: This bit is set to indicate that the level on the SS is inconsistent with the
mode of the SPI (in both master and slave modes).
Serial Peripheral Transmit Register empty flag, SPTE: This bit is set when the transmit buffer is
empty (other data can be loaded is SPDAT). SPTE bit generates transmitter CPU interrupt
request only when SPTEIE is enabled.
Flag
SPIF (SPI data transfer)
MODF (Mode Fault)
SPTE (Transmit register empty)
Note: While using SPTE interruption for “burst mode” transfers (SPTEIE=’1’), the user soft-
ware application should take care to clear SPTEIE, during the last but one data reception (to
be able to generate an interrupt on SPIF flag at the end of the last data reception).
when SS is discarded (SS disabled) it is not possible to detect a MODF error in slave mode
because the SPI is internally selected. Also the SS pin becomes a general purpose I/O.
MOSI
SCK cycle #
SCK
(from master)
(from master)
MISO
(from slave)
SS
(slave)
1
z
0
1
z
0
1
z
0
1
z
0
0
MODF detected
MSB
Request
SPI Transmitter Interrupt Request
SPI mode-fault Interrupt Request
SPI transmit register empty Interrupt Request
0
MSB
MSB
1
MODF detected
B6
B6
2
B5
3
B4
4
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