ATmega1281R231 Atmel Corporation, ATmega1281R231 Datasheet - Page 208

• Manufacturer Part Number: ATmega1281R231
• Manufacturer: Atmel Corporation

Specifications of ATmega1281R231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 16 MHz
• Max I/o Pins: 54
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

22.2.2
22.2.3
2549N–AVR–05/11
Double Speed Operation (U2Xn)
External Clock
Table 22-1.
Note:
Some examples of UBRRn values for some system clock frequencies are found in
page
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has
effect for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the Receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to
External clock input from the XCKn pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
Asynchronous Normal
mode (U2Xn = 0)
Asynchronous Double
Speed mode (U2Xn =
1)
Synchronous Master
mode
Operating Mode
227.
BAUD
f
UBRRn
OSC
1. The baud rate is defined to be the transfer rate in bit per second (bps).
Equations for Calculating Baud Rate Register Setting
Figure 22-2 on page 207
Baud rate (in bits per second, bps).
System Oscillator clock frequency.
Contents of the UBRRHn and UBRRLn Registers, (0-4095).
BAUD
BAUD
BAUD
Equation for Calculating
ATmega640/1280/1281/2560/2561
Baud Rate
=
=
=
----------------------------------------- -
16 UBRRn
-------------------------------------- -
8 UBRRn
-------------------------------------- -
2 UBRRn
(
(
(
for details.
f
f
f
OSC
OSC
OSC
(1)
+
+
+
1
1
1
)
)
)
UBRRn
UBRRn
UBRRn
Equation for Calculating
UBRR Value
=
=
=
----------------------- - 1
16BAUD
------------------- - 1
8BAUD
------------------- - 1
2BAUD
f
f
f
OSC
OSC
OSC
–
–
–
Table 22-9 on
208