ATmega16M1 Automotive Atmel Corporation, ATmega16M1 Automotive Datasheet - Page 235
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ATmega16M1 Automotive
Manufacturer Part Number
ATmega16M1 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATMEGA16M1_AUTOMOTIVE.pdf
(12 pages)
3.ATMEGA16M1_AUTOMOTIVE.pdf
(25 pages)
4.ATMEGA16M1_AUTOMOTIVE.pdf
(367 pages)
Specifications of ATmega16M1 Automotive
Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #2
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #3
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #4
- Current page: 235 of 367
- Download datasheet (7Mb)
18.5
7647G–AVR–09/11
Changing Channel or Reference Selection
Figure 18-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 18-7. ADC Timing Diagram, Free Running Conversion
Table 18-1.
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and reference
selection only takes place at a safe point during the conversion. The channel and reference
selection is continuously updated until a conversion is started. Once the conversion starts, the
channel and reference selection is locked to ensure a sufficient sampling time for the ADC.
Continuous updating resumes in the last eight ADC clock cycle before the conversion com-
pletes (ADIF in ADCSRA is set). Note that the conversion starts on the second following rising
CPU clock edge after ADSC is written. The user is thus advised not to write new channel or
reference selection values to ADMUX until two ADC clock cycle after ADSC is written.
Condition
Sample & Hold
(Cycles from Start of Conversion)
Conversion Time
(Cycles)
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
ADC Conversion Time
Prescaler
Reset
MUX and REFS
Update
1
2
3
4
Atmel ATmega16/32/64/M1/C1
First Conversion
5
Sample &
Hold
6
13.5
25
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
7
One Conversion
8
Conversion
Complete
One Conversion
12
11
Conversion
Complete
Single Ended
Conversion,
13
12
Normal
15.5
13
3.5
14
14
Next Conversion
1
Sign and MSB of Result
LSB of Result
Sign and MSB of Result
2
MUX and REFS
Update
LSB of Result
Next Conversion
3
1
Prescaler
Reset
Auto Triggered
Sample & Hold
4
Conversion
2
5
16
2
235
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