ATmega48 Automotive Atmel Corporation, ATmega48 Automotive Datasheet - Page 46
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ATmega48 Automotive
Manufacturer Part Number
ATmega48 Automotive
Description
Manufacturer
Atmel Corporation
Specifications of ATmega48 Automotive
Flash (kbytes)
4 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
256
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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9.10
9.10.1
9.10.2
46
Register Description
Atmel ATtiny24/44/84 [Preliminary]
MCUSR – MCU Status Register
WDTCSR – Watchdog Timer Control and Status Register
The MCU Status Register provides information on which reset source caused an MCU Reset.
• Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing
a logical zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing
a logical zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logical zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the
flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then
reset the MCUSR as early as possible in the program. If the register is cleared before another
reset occurs, the source of the reset can be found by examining the Reset Flags.
• Bit 7 – WDIF: Watchdog Timeout Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is con-
figured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit
in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 – WDIE: Watchdog Timeout Interrupt Enable
When this bit is written to logical one, WDE is cleared, and the I-bit in the status register is set,
the watchdog time-out interrupt is enabled. In this mode the corresponding interrupt is exe-
cuted instead of a reset if a time-out in the watchdog timer occurs.
Bit
0x34 (0x54)
Read/Write
Initial Value
Bit
0x21 (0x41)
Read/Write
Initial Value
WDIF
R/W
7
0
R
7
–
0
WDIE
R/W
6
0
R
6
–
0
WDP3
R/W
5
0
R
5
–
0
WDCE
R/W
4
0
R
4
–
0
WDE
WDRF
R/W
R/W
X
3
3
WDP2
R/W
BORF
See Bit Description
R/W
2
0
2
WDP1
R/W
EXTRF
1
0
R/W
1
WDP0
R/W
PORF
0
0
R/W
7701E–AVR–02/11
0
WDTCSR
MCUSR
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