ATtiny25 Automotive Atmel Corporation, ATtiny25 Automotive Datasheet - Page 103
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ATtiny25 Automotive
Manufacturer Part Number
ATtiny25 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY25_AUTOMOTIVE.pdf
(7 pages)
3.ATTINY25_AUTOMOTIVE.pdf
(196 pages)
Specifications of ATtiny25 Automotive
Flash (kbytes)
2 Kbytes
Pin Count
8
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
4
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.12
Eeprom (bytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATTINY25_AUTOMOTIVE PDF datasheet #2
- ATTINY25_AUTOMOTIVE PDF datasheet #3
- Current page: 103 of 225
- Download datasheet (4Mb)
14.8.1
14.9
14.9.1
14.9.2
7701E–AVR–02/11
Modes of Operation
Compare Output Mode and Waveform Generation
Normal Mode
Clear Timer on Compare Match (CTC) Mode
The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM
modes. For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action
on the OC1x Register is to be performed on the next compare match. For compare output
actions in the non-PWM modes refer to
Table 14-2 on page
Table 14-3 on page
A change of the COM1x1:0 bit states will have an effect at the first compare match after the
bits are written. For non-PWM modes, the action can be forced to have immediate effect by
using the 1x strobe bits.
The mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is
defined by the combination of the waveform generation mode (WGM13:0) and compare output
mode (COM1x1:0) bits. The compare output mode bits do not affect the counting sequence,
while the waveform generation mode bits do. The COM1x1:0 bits control whether the PWM
output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM
modes, the COM1x1:0 bits control whether the output should be set, cleared or toggle at a
compare match
For detailed timing information refer to
The simplest mode of operation is the normal mode (WGM13:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 16-bit value (max = 0xFFFF), and then restarts from the
bottom (0x0000). In normal operation, the timer/counter overflow flag (TOV1) will be set on the
same timer clock cycle on which the TCNT1 becomes zero. The TOV1 flag in this case
behaves like a 17th bit, except that it is only set, not cleared. However, when combined with
the timer overflow interrupt that automatically clears the TOV1 flag, the timer resolution can be
increased by software. There are no special cases to consider in the normal mode. A new
counter value can be written anytime.
The input capture unit is easy to use in normal mode. However, observe that the maximum
interval between the external events must not exceed the resolution of the counter. If the inter-
val between events is too long, the timer overflow interrupt or the prescaler must be used to
extend the resolution for the capture unit.
The output compare units can be used to generate interrupts at some given time. Using the
output compare to generate waveforms in normal mode is not recommended because this will
occupy too much CPU time.
In clear timer on compare, or CTC, mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 register is
used to manipulate the counter resolution. In CTC mode, the counter is cleared to zero when
the counter value (TCNT1) matches either OCR1A (WGM13:0 = 4) or ICR1 (WGM13:0 = 12).
OCR1A or ICR1 define the top value for the counter, and hence also its resolution. This mode
allows greater control of the compare match output frequency. It also simplifies the operation
of counting external events.
(“Compare Match Output Unit” on page
113, and for phase correct and phase and frequency correct PWM refer to
114.
Atmel ATtiny24/44/84 [Preliminary]
“Timer/Counter Timing Diagrams” on page
Table 14-1 on page
102)
113. For fast PWM mode refer to
110.
103
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