ATtiny25 Automotive Atmel Corporation, ATtiny25 Automotive Datasheet - Page 78
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ATtiny25 Automotive
Manufacturer Part Number
ATtiny25 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY25_AUTOMOTIVE.pdf
(7 pages)
3.ATTINY25_AUTOMOTIVE.pdf
(196 pages)
Specifications of ATtiny25 Automotive
Flash (kbytes)
2 Kbytes
Pin Count
8
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
4
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.12
Eeprom (bytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATTINY25_AUTOMOTIVE PDF datasheet #2
- ATTINY25_AUTOMOTIVE PDF datasheet #3
- Current page: 78 of 225
- Download datasheet (4Mb)
13.7.3
78
Atmel ATtiny24/44/84 [Preliminary]
Fast PWM Mode
The timing diagram for the CTC mode is shown in
(TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then
counter (TCNT0) is cleared.
Figure 13-5. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the top value by using the
OCF0A flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the top value. However, changing top to a value close to bottom when the counter is running
with no or a low prescaler value must be done with care since the CTC mode does not have
the double buffering feature. If the new value written to OCR0A is lower than the current value
of TCNT0, the counter will miss the compare match. The counter will then have to count to its
maximum value (0xFF) and wrap around starting at 0x00 before the compare match can
occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its log-
ical level on each compare match by setting the compare output mode bits to toggle mode
(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction
for the pin is set to output. The waveform generated will have a maximum frequency of
0
lowing equation:
The variable N represents the prescale factor (1, 8, 64, 256, or 1024).
As for the normal mode of operation, the TOV0 flag is set on the same timer clock cycle on
which the counter counts from max to 0x00.
The fast pulse width modulation, or fast PWM, mode (WGM02:0 = 3 or 7) provides a high-fre-
quency PWM waveform generation option. The fast PWM mode differs from the other PWM
option by its single-slope operation. The counter counts from bottom to top then restarts from
bottom. Top is defined as 0xFF when WGM2:0 = 3, and as OCR0A when WGM2:0 = 7. In
non-inverting compare output mode, the output compare (OC0x) is cleared on the compare
match between TCNT0 and OCR0x, and set at bottom. In inverting compare output mode, the
output is set on compare match and cleared at bottom. Due to the single-slope operation, the
operating frequency of the fast PWM mode can be twice as high as the phase correct PWM
mode that uses dual-slope operation.
f
OCnx
= f
clk_I/O
TCNTn
OCn
(Toggle)
Period
=
/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the fol-
------------------------------------------------------ -
2
N
f
clk_I/O
1
+
1
OCRnx
2
3
Figure 13-5 on page
4
78. The counter value
OCnx Interrupt Flag Set
(COMnx1:0 = 1)
7701E–AVR–02/11
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