ATtiny85 Atmel Corporation, ATtiny85 Datasheet - Page 20

• Manufacturer Part Number: ATtiny85
• Manufacturer: Atmel Corporation

Specifications of ATtiny85

• Flash (kbytes): 8 Kbytes
• Pin Count: 8
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 3
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 6
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

5.4
5.5
5.5.1
5.5.2
20
I/O Memory
Register Description
ATtiny25/45/85
EEARH and EEARL – EEPROM Address Register
EEDR – EEPROM Data Register
The I/O space definition of the ATtiny25/45/85 is shown in
All ATtiny25/45/85 I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32
general purpose working registers and the I/O space. I/O Registers within the address range
0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the
instruction set section for more details. When using the I/O specific commands IN and OUT, the
I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using
LD and ST instructions, 0x20 must be added to these addresses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers contain-
ing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and Peripherals Control Registers are explained in later sections.
• Bits 7:1 – Res: Reserved Bits
These bits are reserved for future use and will always read as 0 in ATtiny25/45/85.
• Bits 8:0 – EEAR[8:0]: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL – specifies the high EEPROM address
in the 128/256/512 bytes EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 127/255/511. The initial value of EEAR is undefined. A proper value must be writ-
ten before the EEPROM may be accessed.
• Bits 7:0 – EEDR[7:0]: EEPROM Data
For the EEPROM write operation the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
Bit
0x1F
0x1E
Bit
Read/Write
Read/Write
Initial Value
Initial Value
Bit
0x1D
Read/Write
Initial Value
EEAR7
EEDR7
R/W
R/W
R
X
7
7
0
7
0
–
EEAR6
EEDR6
R/W
R/W
R
X
6
6
0
6
0
–
EEAR5
EEDR5
R/W
R/W
R
5
5
0
X
5
0
–
EEAR4
EEDR4
R/W
R/W
R
X
4
4
0
4
0
–
EEAR3
EEDR3
R/W
R/W
R
3
3
0
X
3
0
–
“Register Summary” on page
EEAR2
EEDR2
R/W
R/W
R
X
2
2
0
2
0
–
EEAR1
EEDR1
R/W
R/W
R
X
1
1
0
1
0
–
EEAR8
EEAR0
EEDR0
R/W
R/W
R/W
0
0
X
X
0
0
2586N–AVR–04/11
EEARH
205.
EEARL
EEDR