ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 263
ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
- Current page: 263 of 960
- Download datasheet (15Mb)
14.5.15.1
14.5.15.2
14.5.15.3
14.5.15.4
14.5.16
32142A–12/2011
Interrupts
Enabling a generic clock
Disabling a generic clock
Changing clock frequency
Generic clock allocation
Figure 14-10. Generic Clock Generation
A generic clock is enabled by writing a one to the Clock Enable bit (CEN) in the Generic Clock
Control Register (GCCTRL). Each generic clock can individually select a clock source by writing
to the Oscillator Select field (OSCSEL). The source clock can optionally be divided by writing a
one to the Divide Enable bit (DIVEN) and the Division Factor field (DIV), resulting in the output
frequency:
where f
generic clock.
A generic clock is disabled by writing a zero to CEN or entering a sleep mode that disables the
PB clocks. In either case, the generic clock will be switched off on the first falling edge after the
disabling event, to ensure that no glitches occur. After CEN has been written to zero, the bit will
still read as one until the next falling edge occurs, and the clock is actually switched off. When
writing a zero to CEN the other bits in GCCTRL should not be changed until CEN reads as zero,
to avoid glitches on the generic clock. The generic clocks will be automatically re-enabled when
waking from sleep.
When changing the generic clock frequency by changing OSCSEL or DIV, the clock should be
disabled before being re-enabled with the new clock source or division setting. This prevents
glitches during the transition.
The generic clocks are allocated to different functions as shown in the “Generic Clock Allocation”
table in the SCIF Module Configuration section.
The SCIF has the following interrupt sources:
• AE - Access Error:
S ources
G eneric
C lock
– A protected SCIF register was accessed without first being correctly unlocked.
SRC
O S C S E L
is the frequency of the selected source clock, and f
f
S R C
D ivider
D IV
f
GCLK
=
----------------------------
2 DIV
f
SRC
ATUC64/128/256L3/4U
D IV E N
+
0
1
1
S leep C ontroller
GCLK
M ask
is the output frequency of the
C E N
G eneric C lock
f
G C LK
263
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