ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 443
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ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
- Current page: 443 of 960
- Download datasheet (15Mb)
20.6.3.6
20.6.3.7
Figure 20-11. Timeguard Operation
32142A–12/2011
Baud Rate
TXEMPTY
TXRDY
Clock
Write
THR
TXD
Multidrop Mode
Transmitter Timeguard
Start
Bit
D0
D1
The receiver will report parity errors in CSR.PARE, unless parity is disabled. Writing a one to
CR.RSTSTA will clear PARE. See
Figure 20-10. Parity Error
If PAR is either 0x6 or 0x7, the USART runs in Multidrop mode. This mode differentiates data
and address characters. Data has the parity bit zero and addresses have a one. By writing a one
to the Send Address bit (CR.SENDA) the user will cause the next character written to THR to be
transmitted as an address. Receiving a character with a one as parity bit will set PARE.
The timeguard feature enables the USART to interface slow devices by inserting an idle state on
the TXD line in between two characters. This idle state corresponds to a long stop bit, whose
duration is selected by the Timeguard Value field in the Transmitter Timeguard Register
(TTGR.TG). The transmitter will hold the TXD line high for TG bit periods, in addition to the num-
ber of stop bits. As illustrated in
when TG has a non-zero value. If a pending character has been written to THR, the TXRDY bit
will not be set until this characters start bit has been sent. TXEMPTY will remain low until the
timeguard transmission has completed.
D2
Baud Rate
D3
RXRDY
PARE
Clock
Write
RXD
D4
CR
D5
D6
Start
Bit
D7
Parity
D0
Bit
D1
Stop
Bit
D2
TG = 4
D3
Figure
D4
Figure 20-10
D5
20-11, the behavior of TXRDY and TXEMPTY is modified
Start
D6
Bit
D7
D0
Parity
Bad
Bit
D1
Stop
Bit
D2
D3
ATUC64/128/256L3/4U
D4
D5
RSTSTA = 1
D6
D7
Parity
Bit
Stop
Bit
TG = 4
443
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