ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 569
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ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
- Current page: 569 of 960
- Download datasheet (15Mb)
Figure 23-8. Slave Transmitter with Multiple Data Bytes
Figure 23-9. Timing Relationship between TWCK, SR.NAK, and SR.BTF
23.8.4
32142A–12/2011
TCOMP
TXRDY
TWD
Slave Receiver Mode
Write THR (Data n)
NBYTES set to m
S
DADR
SR.NAK
SR.BTF
t
1
TWCK
: (CLK_TWIS period) x 2
TWD
If the TWIS matches an address in which the R/W bit in the TWI address phase transfer is
cleared, it will enter slave receiver mode and clear SR.TRA (note that SR.TRA is cleared one
CLK_TWIS cycle after the relevant address match bit in the same register is set).
After the address phase, the following is repeated:
The TWI transfers require the receiver to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the
1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes to
2. Receive a byte. Set SR.BTF when done.
3. Update NBYTES. If CR.CUP is written to one, NBYTES is incremented, otherwise
4. After a data byte has been received, the slave transmits an ACK or NAK bit. For ordi-
5. If STOP is received, SR.TCOMP will be set.
6. If REPEATED START is received, SR.REP will be set.
receive. This is necessary in order to know which of the received bytes is the PEC byte.
NBYTES can also be used to count the number of bytes received if using DMA.
NBYTES is decremented. NBYTES is usually configured to count downwards if PEC is
used.
nary data bytes, the CR.ACK field controls if an ACK or NAK should be returned. If PEC
is enabled and the last byte received was a PEC byte (indicated by NBYTES equal to
zero), The TWIS will automatically return an ACK if the PEC value was correct, other-
wise a NAK will be returned.
DATA (LSB)
R
A
Write THR (Data n+1)
DATA n
t
1
A
N
Write THR (Data n+m)
DATA n+5
Last data sent
t
1
ATUC64/128/256L3/4U
A
P
DATA n+m
STOP sent by master
N
P
569
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